Abstract

It has been indicated that the path forward for the widespread usage of ferroelectric materials may be considerably facilitated through the reduction of programming voltages to on-chip logic compatible values of < 1 V. Obstacles involve issues related to the scaling of the FEs to lower thickness as well as the presence of an interfacial layer (IL) between the high permittivity FE and the substrate, resulting in wasted voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions to show that ultra-thin FE films deposited on single layer graphene can exhibit polarization switching at ~0.8 V with significant TER.

Abstract

It has been indicated that the path forward for the widespread usage of ferroelectric materials may be considerably facilitated through the reduction of programming voltages to on-chip logic compatible values of < 1 V. Obstacles involve issues related to the scaling of the FEs to lower thickness as well as the presence of an interfacial layer (IL) between the high permittivity FE and the substrate, resulting in wasted voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions to show that ultra-thin FE films deposited on single layer graphene can exhibit polarization switching at ~0.8 V with significant TER.

Abstract

It has been indicated that the path forward for the widespread usage of ferroelectric materials may be considerably facilitated through the reduction of programming voltages to on-chip logic compatible values of < 1 V. Obstacles involve issues related to the scaling of the FEs to lower thickness as well as the presence of an interfacial layer (IL) between the high permittivity FE and the substrate, resulting in wasted voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions to show that ultra-thin FE films deposited on single layer graphene can exhibit polarization switching at ~0.8 V with significant TER.

Abstract

It has been indicated that the path forward for the widespread usage of ferroelectric materials may be considerably facilitated through the reduction of programming voltages to on-chip logic compatible values of < 1 V. Obstacles involve issues related to the scaling of the FEs to lower thickness as well as the presence of an interfacial layer (IL) between the high permittivity FE and the substrate, resulting in wasted voltage across the IL. Here, we show how lower operating voltages along with a higher tunneling electroresistance (TER) could be achieved through IL engineering. We use piezoresponse force microscopy and fabricated ferroelectric tunnel junctions to show that ultra-thin FE films deposited on single layer graphene can exhibit polarization switching at ~0.8 V with significant TER.