Patent
US 8,450,190Defect Selective Passivation in Semiconductor Structures
Yuh-Jen Cheng
US
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Patent
Atlas literature
Patent
US 8,450,190Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Detailed Description [0012] In various semiconductor structures and devices, different semiconductor materials with different crystalline structures are …
FIG. 2E. The combination of the inhibition of the GaN growth of the passivation fillings in etch pits and the lateral 15 and vertical growth of the GaN from the …
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
FIG. 4.
FIGS. 5(a) and 5(b). These two images are taken by switching detection mode from cathodoluminescent detection to scattering electron detection under the same …
FIG. 6. The driving voltage of DP-LED shown in the solid line is slightly lower than the driving voltage shown by the dotted line of R-LED. This slightly lower …
FIG. 25 5 which includes SEM images
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method as in claim 1, where in the etch in g of top surface of the first semiconductor layer uses a molten or aqueous solution of KOH, H-2SO4,-H₃P₄H₂SOg₄ j3PO4, HC l, or a mixture of two or more of KOH, H-284, -H₃P₄SO₄ J₃PO₄ and HC l, in a chemical wet etch in g process
(O rigin al) The method as in claim 1, where in the substrate mate n al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 1, where in the passivation mate ri al is SiO₂ Si3, TiO₂ Ta₂O5, f2 gO₂ MgF₂SiO,iNjQ₂L, TiO,Tag5, HfO2, M gOz, or M gF
(O rigin al) The method as in claim 1, where in the passivation mate ri al is an amorphous mate rial
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes Ga and N
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes N 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 5 of 7
(Orig in al) The method as in claim 1, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing
(Orig in al) A method for semiconductor fabrication, compris ing grow in g a first semiconductor layer of a first semiconductor material that in cludes GaN on a substrate that is made of a substrate mate ri al different from the first semiconductor material, apply in g a chemical wet etch in g process to etch a top surface of the first semiconductor layer in a molten or aqueous etch in g solution to create one or more etch pits on the top surface extend ing in to the first semiconductor layer, where in one or more defects are present underneath each etch pit in side the first semiconductor layer, deposit in g a passivation layer of a passivation mate ri al on the top surface to cover exposed areas of the top surface and the one or more etch pits to cover space above the one or more defects in each etch pit, thinni ng down the passivation layer to remove some of the passivation material to expose at least part of the top surface while leav in g the space above the one or more defects in each etch pit covered by the passivation layer, after the th inni ng down, grow in g the first semiconductor material or a semiconductor compatible with the first semiconductor material on exposed areas of the first semiconductor layer to form a second semiconductor layer that covers the top surface and the one or more etch pits which are covered by the passivation layer to block extension of a defect in the first semiconductor layer in to the second semiconductor layer, and form in g one or more additional semiconductor layers over the second semiconductor layer
(Orig in al) The method as in claim 17, compris ing pattern in g the one or more additional semiconductor layers over the second semiconductor layer to form semiconductor device structures 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 6 of 7
(Orig in al) The method as in claim 17, where in the substrate mate ri al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 17, where in the passivation material is SiO2, Si₃N, mi02, Ta₂O₅ M 2SO02,S₁N4, Ti02,TaO5, HfO2, MgOz, or Mg F₂
(Orig in al) The method as in claim 17, where in the passivation material is an amorphous material
The method as in claim 17, where in the molten or aqueous etch in g solution inc ludes KOH, 42S04- 4-394H₂SO4,HPO4, HC l, or a mixture of two or more of KOH, H-2SO4,-H₃P'fHSO4,H₃PO₄ and HCl
(Orig in al) The method as in claim 17, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing Claims 24-28 Canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
reduced-defect semiconductor structure
Materials described outside the worked examples.
KOH
H₂SO₄
H₃PO₄
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8-0cm | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,450,190Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Detailed Description [0012] In various semiconductor structures and devices, different semiconductor materials with different crystalline structures are …
FIG. 2E. The combination of the inhibition of the GaN growth of the passivation fillings in etch pits and the lateral 15 and vertical growth of the GaN from the …
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
FIG. 4.
FIGS. 5(a) and 5(b). These two images are taken by switching detection mode from cathodoluminescent detection to scattering electron detection under the same …
FIG. 6. The driving voltage of DP-LED shown in the solid line is slightly lower than the driving voltage shown by the dotted line of R-LED. This slightly lower …
FIG. 25 5 which includes SEM images
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method as in claim 1, where in the etch in g of top surface of the first semiconductor layer uses a molten or aqueous solution of KOH, H-2SO4,-H₃P₄H₂SOg₄ j3PO4, HC l, or a mixture of two or more of KOH, H-284, -H₃P₄SO₄ J₃PO₄ and HC l, in a chemical wet etch in g process
(O rigin al) The method as in claim 1, where in the substrate mate n al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 1, where in the passivation mate ri al is SiO₂ Si3, TiO₂ Ta₂O5, f2 gO₂ MgF₂SiO,iNjQ₂L, TiO,Tag5, HfO2, M gOz, or M gF
(O rigin al) The method as in claim 1, where in the passivation mate ri al is an amorphous mate rial
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes Ga and N
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes N 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 5 of 7
(Orig in al) The method as in claim 1, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing
(Orig in al) A method for semiconductor fabrication, compris ing grow in g a first semiconductor layer of a first semiconductor material that in cludes GaN on a substrate that is made of a substrate mate ri al different from the first semiconductor material, apply in g a chemical wet etch in g process to etch a top surface of the first semiconductor layer in a molten or aqueous etch in g solution to create one or more etch pits on the top surface extend ing in to the first semiconductor layer, where in one or more defects are present underneath each etch pit in side the first semiconductor layer, deposit in g a passivation layer of a passivation mate ri al on the top surface to cover exposed areas of the top surface and the one or more etch pits to cover space above the one or more defects in each etch pit, thinni ng down the passivation layer to remove some of the passivation material to expose at least part of the top surface while leav in g the space above the one or more defects in each etch pit covered by the passivation layer, after the th inni ng down, grow in g the first semiconductor material or a semiconductor compatible with the first semiconductor material on exposed areas of the first semiconductor layer to form a second semiconductor layer that covers the top surface and the one or more etch pits which are covered by the passivation layer to block extension of a defect in the first semiconductor layer in to the second semiconductor layer, and form in g one or more additional semiconductor layers over the second semiconductor layer
(Orig in al) The method as in claim 17, compris ing pattern in g the one or more additional semiconductor layers over the second semiconductor layer to form semiconductor device structures 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 6 of 7
(Orig in al) The method as in claim 17, where in the substrate mate ri al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 17, where in the passivation material is SiO2, Si₃N, mi02, Ta₂O₅ M 2SO02,S₁N4, Ti02,TaO5, HfO2, MgOz, or Mg F₂
(Orig in al) The method as in claim 17, where in the passivation material is an amorphous material
The method as in claim 17, where in the molten or aqueous etch in g solution inc ludes KOH, 42S04- 4-394H₂SO4,HPO4, HC l, or a mixture of two or more of KOH, H-2SO4,-H₃P'fHSO4,H₃PO₄ and HCl
(Orig in al) The method as in claim 17, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing Claims 24-28 Canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
reduced-defect semiconductor structure
Materials described outside the worked examples.
KOH
H₂SO₄
H₃PO₄
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8-0cm | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,450,190Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Detailed Description [0012] In various semiconductor structures and devices, different semiconductor materials with different crystalline structures are …
FIG. 2E. The combination of the inhibition of the GaN growth of the passivation fillings in etch pits and the lateral 15 and vertical growth of the GaN from the …
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
FIG. 4.
FIGS. 5(a) and 5(b). These two images are taken by switching detection mode from cathodoluminescent detection to scattering electron detection under the same …
FIG. 6. The driving voltage of DP-LED shown in the solid line is slightly lower than the driving voltage shown by the dotted line of R-LED. This slightly lower …
FIG. 25 5 which includes SEM images
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method as in claim 1, where in the etch in g of top surface of the first semiconductor layer uses a molten or aqueous solution of KOH, H-2SO4,-H₃P₄H₂SOg₄ j3PO4, HC l, or a mixture of two or more of KOH, H-284, -H₃P₄SO₄ J₃PO₄ and HC l, in a chemical wet etch in g process
(O rigin al) The method as in claim 1, where in the substrate mate n al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 1, where in the passivation mate ri al is SiO₂ Si3, TiO₂ Ta₂O5, f2 gO₂ MgF₂SiO,iNjQ₂L, TiO,Tag5, HfO2, M gOz, or M gF
(O rigin al) The method as in claim 1, where in the passivation mate ri al is an amorphous mate rial
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes Ga and N
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes N 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 5 of 7
(Orig in al) The method as in claim 1, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing
(Orig in al) A method for semiconductor fabrication, compris ing grow in g a first semiconductor layer of a first semiconductor material that in cludes GaN on a substrate that is made of a substrate mate ri al different from the first semiconductor material, apply in g a chemical wet etch in g process to etch a top surface of the first semiconductor layer in a molten or aqueous etch in g solution to create one or more etch pits on the top surface extend ing in to the first semiconductor layer, where in one or more defects are present underneath each etch pit in side the first semiconductor layer, deposit in g a passivation layer of a passivation mate ri al on the top surface to cover exposed areas of the top surface and the one or more etch pits to cover space above the one or more defects in each etch pit, thinni ng down the passivation layer to remove some of the passivation material to expose at least part of the top surface while leav in g the space above the one or more defects in each etch pit covered by the passivation layer, after the th inni ng down, grow in g the first semiconductor material or a semiconductor compatible with the first semiconductor material on exposed areas of the first semiconductor layer to form a second semiconductor layer that covers the top surface and the one or more etch pits which are covered by the passivation layer to block extension of a defect in the first semiconductor layer in to the second semiconductor layer, and form in g one or more additional semiconductor layers over the second semiconductor layer
(Orig in al) The method as in claim 17, compris ing pattern in g the one or more additional semiconductor layers over the second semiconductor layer to form semiconductor device structures 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 6 of 7
(Orig in al) The method as in claim 17, where in the substrate mate ri al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 17, where in the passivation material is SiO2, Si₃N, mi02, Ta₂O₅ M 2SO02,S₁N4, Ti02,TaO5, HfO2, MgOz, or Mg F₂
(Orig in al) The method as in claim 17, where in the passivation material is an amorphous material
The method as in claim 17, where in the molten or aqueous etch in g solution inc ludes KOH, 42S04- 4-394H₂SO4,HPO4, HC l, or a mixture of two or more of KOH, H-2SO4,-H₃P'fHSO4,H₃PO₄ and HCl
(Orig in al) The method as in claim 17, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing Claims 24-28 Canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
reduced-defect semiconductor structure
Materials described outside the worked examples.
KOH
H₂SO₄
H₃PO₄
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8-0cm | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,450,190Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Detailed Description [0012] In various semiconductor structures and devices, different semiconductor materials with different crystalline structures are …
FIG. 2E. The combination of the inhibition of the GaN growth of the passivation fillings in etch pits and the lateral 15 and vertical growth of the GaN from the …
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
FIG. 4.
FIGS. 5(a) and 5(b). These two images are taken by switching detection mode from cathodoluminescent detection to scattering electron detection under the same …
FIG. 6. The driving voltage of DP-LED shown in the solid line is slightly lower than the driving voltage shown by the dotted line of R-LED. This slightly lower …
FIG. 25 5 which includes SEM images
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method as in claim 1, where in the etch in g of top surface of the first semiconductor layer uses a molten or aqueous solution of KOH, H-2SO4,-H₃P₄H₂SOg₄ j3PO4, HC l, or a mixture of two or more of KOH, H-284, -H₃P₄SO₄ J₃PO₄ and HC l, in a chemical wet etch in g process
(O rigin al) The method as in claim 1, where in the substrate mate n al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 1, where in the passivation mate ri al is SiO₂ Si3, TiO₂ Ta₂O5, f2 gO₂ MgF₂SiO,iNjQ₂L, TiO,Tag5, HfO2, M gOz, or M gF
(O rigin al) The method as in claim 1, where in the passivation mate ri al is an amorphous mate rial
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes Ga and N
(O rigin al) The method as in claim 1, where in the first semiconductor mate n al is a semiconductor that in cludes N 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 5 of 7
(Orig in al) The method as in claim 1, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing
(Orig in al) A method for semiconductor fabrication, compris ing grow in g a first semiconductor layer of a first semiconductor material that in cludes GaN on a substrate that is made of a substrate mate ri al different from the first semiconductor material, apply in g a chemical wet etch in g process to etch a top surface of the first semiconductor layer in a molten or aqueous etch in g solution to create one or more etch pits on the top surface extend ing in to the first semiconductor layer, where in one or more defects are present underneath each etch pit in side the first semiconductor layer, deposit in g a passivation layer of a passivation mate ri al on the top surface to cover exposed areas of the top surface and the one or more etch pits to cover space above the one or more defects in each etch pit, thinni ng down the passivation layer to remove some of the passivation material to expose at least part of the top surface while leav in g the space above the one or more defects in each etch pit covered by the passivation layer, after the th inni ng down, grow in g the first semiconductor material or a semiconductor compatible with the first semiconductor material on exposed areas of the first semiconductor layer to form a second semiconductor layer that covers the top surface and the one or more etch pits which are covered by the passivation layer to block extension of a defect in the first semiconductor layer in to the second semiconductor layer, and form in g one or more additional semiconductor layers over the second semiconductor layer
(Orig in al) The method as in claim 17, compris ing pattern in g the one or more additional semiconductor layers over the second semiconductor layer to form semiconductor device structures 09069-8002 US00/LEGAL₂₆₂₈₂₅₂₄ 1 App li cants Yuh-Jen Cheng et al Docket No 09069-8002 US 00 App l No 12/729,698 Filed Page 6 of 7
(Orig in al) The method as in claim 17, where in the substrate mate ri al is sapphire, si li con carbide, si li con, gal lium arse ni de, li thium gallate, or z inc oxide
The method as in claim 17, where in the passivation material is SiO2, Si₃N, mi02, Ta₂O₅ M 2SO02,S₁N4, Ti02,TaO5, HfO2, MgOz, or Mg F₂
(Orig in al) The method as in claim 17, where in the passivation material is an amorphous material
The method as in claim 17, where in the molten or aqueous etch in g solution inc ludes KOH, 42S04- 4-394H₂SO4,HPO4, HC l, or a mixture of two or more of KOH, H-2SO4,-H₃P'fHSO4,H₃PO₄ and HCl
(Orig in al) The method as in claim 17, where in the th inni ng down of the passivation layer to remove some of the passivation material in cludes chemical mecha ni cal po lishin g, in ductively charged plasmas etch in g, or in ductively charged plasma reactive ion etch ing Claims 24-28 Canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
reduced-defect semiconductor structure
Materials described outside the worked examples.
KOH
H₂SO₄
H₃PO₄
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3(a) shows the SEM image of the GaN surface after the selective etching corresponding to the processing step in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8-0cm | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
HCl
mixture of KOH, H₂SO4, H₃PO4, HCl
sapphire
Al₂O₃
silicon carbide
SiC
silicon
Si
gallium arsenide
GaAs
lithium gallate
LiGaO₂
zinc oxide
ZnO
SiO₂
Si₃N₄
TiO₂
Ta₂O₅
HfO₂
MgO
MgF₂
amorphous passivation material
semiconductor including Ga and N
semiconductor including N
GaN
passivation material (generic)
Group III-V semiconductor
FIG. 4.
FIG. 4.
FIG. 25 5 which includes SEM images
| — |
HCl
mixture of KOH, H₂SO4, H₃PO4, HCl
sapphire
Al₂O₃
silicon carbide
SiC
silicon
Si
gallium arsenide
GaAs
lithium gallate
LiGaO₂
zinc oxide
ZnO
SiO₂
Si₃N₄
TiO₂
Ta₂O₅
HfO₂
MgO
MgF₂
amorphous passivation material
semiconductor including Ga and N
semiconductor including N
GaN
passivation material (generic)
Group III-V semiconductor
FIG. 4.
FIG. 4.
FIG. 25 5 which includes SEM images
| — |
HCl
mixture of KOH, H₂SO4, H₃PO4, HCl
sapphire
Al₂O₃
silicon carbide
SiC
silicon
Si
gallium arsenide
GaAs
lithium gallate
LiGaO₂
zinc oxide
ZnO
SiO₂
Si₃N₄
TiO₂
Ta₂O₅
HfO₂
MgO
MgF₂
amorphous passivation material
semiconductor including Ga and N
semiconductor including N
GaN
passivation material (generic)
Group III-V semiconductor
FIG. 4.
FIG. 4.
FIG. 25 5 which includes SEM images
| — |
HCl
mixture of KOH, H₂SO4, H₃PO4, HCl
sapphire
Al₂O₃
silicon carbide
SiC
silicon
Si
gallium arsenide
GaAs
lithium gallate
LiGaO₂
zinc oxide
ZnO
SiO₂
Si₃N₄
TiO₂
Ta₂O₅
HfO₂
MgO
MgF₂
amorphous passivation material
semiconductor including Ga and N
semiconductor including N
GaN
passivation material (generic)
Group III-V semiconductor
FIG. 4.
FIG. 4.
FIG. 25 5 which includes SEM images
| — |