Patent
US 9,197,245DIGITAL SERIAL-TO-PARALLEL CONVERTER AND GaAs MMIC USING THE SAME
Jin-Cheol JEONG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
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US 9,197,245Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a configuration of a digital serial-to-parallel converter and a configuration of a GaAs MMIC according to an exemplary 4 PA₁₉₅₇- …
FIG. 2 is an internal configuration diagram of a buffer illustrated in
FIG. 3 is an internal configuration diagram of a D flip flop illustrated in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital serial-to-parallel converter, comprising: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals, wherein the plurality of D flip flops each include a plurality of 2-input NOR gates and one 3-input NOR gate.
The digital serial-to-parallel converter of claim 1, wherein the plurality of D flip flops are each operated by one input signal and one output signal.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers each include two inverters which are connected in series.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers output a control signal for controlling a digital phase shifter and a digital attenuator as the complementary signal.
The digital serial-to-parallel converter of claim 1, further comprising: an output driver configured to generate a control signal for controlling a digital phase shifter and a digital attenuator based on the complementary signals from the plurality of buffers and transmit the generated control signal to a digital phase shifting and attenuating controller which controls the digital phase shifter and the digital attenuator.
The digital serial-to-parallel converter of claim 1, further comprising: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; Page 3 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal; and a second output driver configured to generate a control signal for controlling a transmitting and receiving switch based on the complementary signal from the buffer and transmit the generated control signal to a transmitting and receiving switch controller for controlling the transmitting and receiving switch.
canceled
A GaAs MMIC, comprising: a digital serial-to-parallel converter including a first converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal, a plurality of D flip flops configured to transmit the serial data received through the first converter to a D flip flop of a next stage by the clock signal received through the first converter and output the serial data of the D flip flop of the next stage by the load signal received through the first converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals; a digital phase shifter configured to be operated according to a control signal based on the complementary signals from the plurality of buffers; and a digital attenuator configured to be operated according to a control signal based on the complementary signals from the plurality of buffers.
The GaAs MMIC of claim 10, wherein the digital serial-to-parallel converter further includes: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; and Page 4 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal.
Layer stacks claimed or described, ordered top of device to substrate.
digital serial-to-parallel converter
No layer stack recorded.
GaAs MMIC with digital serial-to-parallel converter, digital phase shifter, digital attenuator, and transmitting/receiving switch
No layer stack recorded.
Materials described outside the worked examples.
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,197,245Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a configuration of a digital serial-to-parallel converter and a configuration of a GaAs MMIC according to an exemplary 4 PA₁₉₅₇- …
FIG. 2 is an internal configuration diagram of a buffer illustrated in
FIG. 3 is an internal configuration diagram of a D flip flop illustrated in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital serial-to-parallel converter, comprising: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals, wherein the plurality of D flip flops each include a plurality of 2-input NOR gates and one 3-input NOR gate.
The digital serial-to-parallel converter of claim 1, wherein the plurality of D flip flops are each operated by one input signal and one output signal.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers each include two inverters which are connected in series.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers output a control signal for controlling a digital phase shifter and a digital attenuator as the complementary signal.
The digital serial-to-parallel converter of claim 1, further comprising: an output driver configured to generate a control signal for controlling a digital phase shifter and a digital attenuator based on the complementary signals from the plurality of buffers and transmit the generated control signal to a digital phase shifting and attenuating controller which controls the digital phase shifter and the digital attenuator.
The digital serial-to-parallel converter of claim 1, further comprising: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; Page 3 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal; and a second output driver configured to generate a control signal for controlling a transmitting and receiving switch based on the complementary signal from the buffer and transmit the generated control signal to a transmitting and receiving switch controller for controlling the transmitting and receiving switch.
canceled
A GaAs MMIC, comprising: a digital serial-to-parallel converter including a first converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal, a plurality of D flip flops configured to transmit the serial data received through the first converter to a D flip flop of a next stage by the clock signal received through the first converter and output the serial data of the D flip flop of the next stage by the load signal received through the first converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals; a digital phase shifter configured to be operated according to a control signal based on the complementary signals from the plurality of buffers; and a digital attenuator configured to be operated according to a control signal based on the complementary signals from the plurality of buffers.
The GaAs MMIC of claim 10, wherein the digital serial-to-parallel converter further includes: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; and Page 4 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal.
Layer stacks claimed or described, ordered top of device to substrate.
digital serial-to-parallel converter
No layer stack recorded.
GaAs MMIC with digital serial-to-parallel converter, digital phase shifter, digital attenuator, and transmitting/receiving switch
No layer stack recorded.
Materials described outside the worked examples.
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,197,245Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a configuration of a digital serial-to-parallel converter and a configuration of a GaAs MMIC according to an exemplary 4 PA₁₉₅₇- …
FIG. 2 is an internal configuration diagram of a buffer illustrated in
FIG. 3 is an internal configuration diagram of a D flip flop illustrated in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital serial-to-parallel converter, comprising: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals, wherein the plurality of D flip flops each include a plurality of 2-input NOR gates and one 3-input NOR gate.
The digital serial-to-parallel converter of claim 1, wherein the plurality of D flip flops are each operated by one input signal and one output signal.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers each include two inverters which are connected in series.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers output a control signal for controlling a digital phase shifter and a digital attenuator as the complementary signal.
The digital serial-to-parallel converter of claim 1, further comprising: an output driver configured to generate a control signal for controlling a digital phase shifter and a digital attenuator based on the complementary signals from the plurality of buffers and transmit the generated control signal to a digital phase shifting and attenuating controller which controls the digital phase shifter and the digital attenuator.
The digital serial-to-parallel converter of claim 1, further comprising: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; Page 3 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal; and a second output driver configured to generate a control signal for controlling a transmitting and receiving switch based on the complementary signal from the buffer and transmit the generated control signal to a transmitting and receiving switch controller for controlling the transmitting and receiving switch.
canceled
A GaAs MMIC, comprising: a digital serial-to-parallel converter including a first converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal, a plurality of D flip flops configured to transmit the serial data received through the first converter to a D flip flop of a next stage by the clock signal received through the first converter and output the serial data of the D flip flop of the next stage by the load signal received through the first converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals; a digital phase shifter configured to be operated according to a control signal based on the complementary signals from the plurality of buffers; and a digital attenuator configured to be operated according to a control signal based on the complementary signals from the plurality of buffers.
The GaAs MMIC of claim 10, wherein the digital serial-to-parallel converter further includes: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; and Page 4 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal.
Layer stacks claimed or described, ordered top of device to substrate.
digital serial-to-parallel converter
No layer stack recorded.
GaAs MMIC with digital serial-to-parallel converter, digital phase shifter, digital attenuator, and transmitting/receiving switch
No layer stack recorded.
Materials described outside the worked examples.
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,197,245Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a configuration of a digital serial-to-parallel converter and a configuration of a GaAs MMIC according to an exemplary 4 PA₁₉₅₇- …
FIG. 2 is an internal configuration diagram of a buffer illustrated in
FIG. 3 is an internal configuration diagram of a D flip flop illustrated in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital serial-to-parallel converter, comprising: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals, wherein the plurality of D flip flops each include a plurality of 2-input NOR gates and one 3-input NOR gate.
The digital serial-to-parallel converter of claim 1, wherein the plurality of D flip flops are each operated by one input signal and one output signal.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers each include two inverters which are connected in series.
The digital serial-to-parallel converter of claim 1, wherein the plurality of buffers output a control signal for controlling a digital phase shifter and a digital attenuator as the complementary signal.
The digital serial-to-parallel converter of claim 1, further comprising: an output driver configured to generate a control signal for controlling a digital phase shifter and a digital attenuator based on the complementary signals from the plurality of buffers and transmit the generated control signal to a digital phase shifting and attenuating controller which controls the digital phase shifter and the digital attenuator.
The digital serial-to-parallel converter of claim 1, further comprising: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; Page 3 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal; and a second output driver configured to generate a control signal for controlling a transmitting and receiving switch based on the complementary signal from the buffer and transmit the generated control signal to a transmitting and receiving switch controller for controlling the transmitting and receiving switch.
canceled
A GaAs MMIC, comprising: a digital serial-to-parallel converter including a first converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal, a plurality of D flip flops configured to transmit the serial data received through the first converter to a D flip flop of a next stage by the clock signal received through the first converter and output the serial data of the D flip flop of the next stage by the load signal received through the first converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals; a digital phase shifter configured to be operated according to a control signal based on the complementary signals from the plurality of buffers; and a digital attenuator configured to be operated according to a control signal based on the complementary signals from the plurality of buffers.
The GaAs MMIC of claim 10, wherein the digital serial-to-parallel converter further includes: a second converter configured to convert a switch signal input to the TTL into the DCFL signal; and Page 4 of 7 U.S. Serial No.: 14/515,112 PATENT DOCKET: PA 1 957-0 a buffer configured to receive the switch signal through the second converter to generate and output the complementary signal.
Layer stacks claimed or described, ordered top of device to substrate.
digital serial-to-parallel converter
No layer stack recorded.
GaAs MMIC with digital serial-to-parallel converter, digital phase shifter, digital attenuator, and transmitting/receiving switch
No layer stack recorded.
Materials described outside the worked examples.
GaAs
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