Patent
US 11,171,226IGBT SEMICONDUCTOR STRUCTURE
Volker DUDEK
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,171,226Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 2 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 3 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 4 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 5 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 6 shows a schematic view of an embodiment according to the invention of an IGBT.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An IGBT semiconductor structure comprising: a p + substrate formed on a bottom of the IGBT semiconductor structure with a dopant concentration of 5-10 18-5-10 2 0 cm⁻³, a layer thickness of 50-500 p m, and that includes a GaAs compound or is made of a GaAs compound; an n- layer with a dopant concentration of 10 12 -10 17 cm⁻³, a layer thickness of 10-300 p m, and that includes a GaAs compound or is made of a GaAs compound; at least one p region arranged adjacent to the n- layer with a dopant concentration of 1 0 14-10 18 cm 3, and that includes a GaAs compound or is made of a GaAs compound; at least one n + region arranged adjacent to the p region with a dopant concentration of at least 10 19 cm⁻³, and that includes a GaAs compound or is made of a GaAs compound; a dielectric layer; a first terminal contact connected in an electrically conductive manner to the bottom of the IGBT semiconductor structure, the first terminal contact includes a metal or a metal compound or is made of a metal or a metal compound; a second terminal contact and a third terminal contact, each of which includes a metal or a metal compound or is made of a metal or a metal compound; wherein the at least one p region forms a first p-n junction together with the n- layer; wherein the at least one n+ region forms a second p-n junction together with the at least one p region; wherein the dielectric layer covers at least the first p-n junction and the second p-n junction and is integrally joined to the n- l ayer, the p region, and the n + region, wherein the second terminal contact is a field plate on the dielectric layer, wherein the third terminal contact is connected in an electrically conductive manner to the at least one p region and the at least one n + region, wherein a doped intermediate layer with a layer thickness of 1 pm-50 pm and a dopant concentration of 10 12 -10 17 cm 3 is arranged between the p + substrate and the n-l ayer, the doped intermediate layer being integrally joined to at least the p + substrate, wherein a total height of the IGBT semiconductor structure is a maximum of 150- 500 pm, [[and]] wherein the dielectric layer includes a deposited oxide and has a layer thickness from 10 nm to 1 pm, and wherein the IGBT semiconductor structure has a trench extending from a top of the IGBT semiconductor structure through the n + region and the p region into the n- layer. Currently amended
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is p-doped. Original
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is n-doped. Original
Original
Layer stacks claimed or described, ordered top of device to substrate.
IGBT semiconductor structure (trench-gate, GaAs-based)
Materials described outside the worked examples.
p+ substrate (GaAs compound)
GaAs
doped intermediate layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–15 mm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,171,226Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 2 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 3 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 4 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 5 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 6 shows a schematic view of an embodiment according to the invention of an IGBT.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An IGBT semiconductor structure comprising: a p + substrate formed on a bottom of the IGBT semiconductor structure with a dopant concentration of 5-10 18-5-10 2 0 cm⁻³, a layer thickness of 50-500 p m, and that includes a GaAs compound or is made of a GaAs compound; an n- layer with a dopant concentration of 10 12 -10 17 cm⁻³, a layer thickness of 10-300 p m, and that includes a GaAs compound or is made of a GaAs compound; at least one p region arranged adjacent to the n- layer with a dopant concentration of 1 0 14-10 18 cm 3, and that includes a GaAs compound or is made of a GaAs compound; at least one n + region arranged adjacent to the p region with a dopant concentration of at least 10 19 cm⁻³, and that includes a GaAs compound or is made of a GaAs compound; a dielectric layer; a first terminal contact connected in an electrically conductive manner to the bottom of the IGBT semiconductor structure, the first terminal contact includes a metal or a metal compound or is made of a metal or a metal compound; a second terminal contact and a third terminal contact, each of which includes a metal or a metal compound or is made of a metal or a metal compound; wherein the at least one p region forms a first p-n junction together with the n- layer; wherein the at least one n+ region forms a second p-n junction together with the at least one p region; wherein the dielectric layer covers at least the first p-n junction and the second p-n junction and is integrally joined to the n- l ayer, the p region, and the n + region, wherein the second terminal contact is a field plate on the dielectric layer, wherein the third terminal contact is connected in an electrically conductive manner to the at least one p region and the at least one n + region, wherein a doped intermediate layer with a layer thickness of 1 pm-50 pm and a dopant concentration of 10 12 -10 17 cm 3 is arranged between the p + substrate and the n-l ayer, the doped intermediate layer being integrally joined to at least the p + substrate, wherein a total height of the IGBT semiconductor structure is a maximum of 150- 500 pm, [[and]] wherein the dielectric layer includes a deposited oxide and has a layer thickness from 10 nm to 1 pm, and wherein the IGBT semiconductor structure has a trench extending from a top of the IGBT semiconductor structure through the n + region and the p region into the n- layer. Currently amended
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is p-doped. Original
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is n-doped. Original
Original
Layer stacks claimed or described, ordered top of device to substrate.
IGBT semiconductor structure (trench-gate, GaAs-based)
Materials described outside the worked examples.
p+ substrate (GaAs compound)
GaAs
doped intermediate layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–15 mm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,171,226Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 2 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 3 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 4 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 5 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 6 shows a schematic view of an embodiment according to the invention of an IGBT.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An IGBT semiconductor structure comprising: a p + substrate formed on a bottom of the IGBT semiconductor structure with a dopant concentration of 5-10 18-5-10 2 0 cm⁻³, a layer thickness of 50-500 p m, and that includes a GaAs compound or is made of a GaAs compound; an n- layer with a dopant concentration of 10 12 -10 17 cm⁻³, a layer thickness of 10-300 p m, and that includes a GaAs compound or is made of a GaAs compound; at least one p region arranged adjacent to the n- layer with a dopant concentration of 1 0 14-10 18 cm 3, and that includes a GaAs compound or is made of a GaAs compound; at least one n + region arranged adjacent to the p region with a dopant concentration of at least 10 19 cm⁻³, and that includes a GaAs compound or is made of a GaAs compound; a dielectric layer; a first terminal contact connected in an electrically conductive manner to the bottom of the IGBT semiconductor structure, the first terminal contact includes a metal or a metal compound or is made of a metal or a metal compound; a second terminal contact and a third terminal contact, each of which includes a metal or a metal compound or is made of a metal or a metal compound; wherein the at least one p region forms a first p-n junction together with the n- layer; wherein the at least one n+ region forms a second p-n junction together with the at least one p region; wherein the dielectric layer covers at least the first p-n junction and the second p-n junction and is integrally joined to the n- l ayer, the p region, and the n + region, wherein the second terminal contact is a field plate on the dielectric layer, wherein the third terminal contact is connected in an electrically conductive manner to the at least one p region and the at least one n + region, wherein a doped intermediate layer with a layer thickness of 1 pm-50 pm and a dopant concentration of 10 12 -10 17 cm 3 is arranged between the p + substrate and the n-l ayer, the doped intermediate layer being integrally joined to at least the p + substrate, wherein a total height of the IGBT semiconductor structure is a maximum of 150- 500 pm, [[and]] wherein the dielectric layer includes a deposited oxide and has a layer thickness from 10 nm to 1 pm, and wherein the IGBT semiconductor structure has a trench extending from a top of the IGBT semiconductor structure through the n + region and the p region into the n- layer. Currently amended
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is p-doped. Original
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is n-doped. Original
Original
Layer stacks claimed or described, ordered top of device to substrate.
IGBT semiconductor structure (trench-gate, GaAs-based)
Materials described outside the worked examples.
p+ substrate (GaAs compound)
GaAs
doped intermediate layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–15 mm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,171,226Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 2 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 3 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 4 shows a schematic view of an embodiment according to the invention of an IGBT, [0
Figure 5 shows a schematic top view of an embodiment according to the invention of an IGBT, [0
Figure 6 shows a schematic view of an embodiment according to the invention of an IGBT.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An IGBT semiconductor structure comprising: a p + substrate formed on a bottom of the IGBT semiconductor structure with a dopant concentration of 5-10 18-5-10 2 0 cm⁻³, a layer thickness of 50-500 p m, and that includes a GaAs compound or is made of a GaAs compound; an n- layer with a dopant concentration of 10 12 -10 17 cm⁻³, a layer thickness of 10-300 p m, and that includes a GaAs compound or is made of a GaAs compound; at least one p region arranged adjacent to the n- layer with a dopant concentration of 1 0 14-10 18 cm 3, and that includes a GaAs compound or is made of a GaAs compound; at least one n + region arranged adjacent to the p region with a dopant concentration of at least 10 19 cm⁻³, and that includes a GaAs compound or is made of a GaAs compound; a dielectric layer; a first terminal contact connected in an electrically conductive manner to the bottom of the IGBT semiconductor structure, the first terminal contact includes a metal or a metal compound or is made of a metal or a metal compound; a second terminal contact and a third terminal contact, each of which includes a metal or a metal compound or is made of a metal or a metal compound; wherein the at least one p region forms a first p-n junction together with the n- layer; wherein the at least one n+ region forms a second p-n junction together with the at least one p region; wherein the dielectric layer covers at least the first p-n junction and the second p-n junction and is integrally joined to the n- l ayer, the p region, and the n + region, wherein the second terminal contact is a field plate on the dielectric layer, wherein the third terminal contact is connected in an electrically conductive manner to the at least one p region and the at least one n + region, wherein a doped intermediate layer with a layer thickness of 1 pm-50 pm and a dopant concentration of 10 12 -10 17 cm 3 is arranged between the p + substrate and the n-l ayer, the doped intermediate layer being integrally joined to at least the p + substrate, wherein a total height of the IGBT semiconductor structure is a maximum of 150- 500 pm, [[and]] wherein the dielectric layer includes a deposited oxide and has a layer thickness from 10 nm to 1 pm, and wherein the IGBT semiconductor structure has a trench extending from a top of the IGBT semiconductor structure through the n + region and the p region into the n- layer. Currently amended
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is p-doped. Original
The IGBT semiconductor structure according to claim 1, wherein the intermediate layer is n-doped. Original
Original
Layer stacks claimed or described, ordered top of device to substrate.
IGBT semiconductor structure (trench-gate, GaAs-based)
Materials described outside the worked examples.
p+ substrate (GaAs compound)
GaAs
doped intermediate layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–15 mm | — |
Related documents with shared materials, methods, properties, or citations.
dielectric layer (deposited oxide)
terminal contact metal or metal compound
Multiphysics Modeling on Photoconductive Antennas for Terahertz Applications
dielectric layer (deposited oxide)
terminal contact metal or metal compound
Multiphysics Modeling on Photoconductive Antennas for Terahertz Applications
dielectric layer (deposited oxide)
terminal contact metal or metal compound
Multiphysics Modeling on Photoconductive Antennas for Terahertz Applications
dielectric layer (deposited oxide)
terminal contact metal or metal compound
Multiphysics Modeling on Photoconductive Antennas for Terahertz Applications