Patent
US 8,440,467ELECTRONIC SWITCHING, MEMORY, AND SENSOR DEVICES FROM CARBON SHEETS ON DIELECTRIC MATERIALS
James M. Tour, Yubao Li, Alexander Sinitskiy
US
Copyright © 2026 Matter42. All rights reserved.
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US 8,440,467Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an embodiment of C-Si O 2-SiC, C- Si₀ 2-Si, and C-Si O 2 nanocables.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Figure 3 shows a selected-area electron diffraction pattern of a C- Si₀ 2-SiC nanocable embodiment.
Figure 4 shows a n embodiment of a two-terminal electronic device and exemplary process steps for preparing the device.
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 7 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various long channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 8 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various short channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 9 shows an embodiment of a reverse bias sweep of +15 V to -15 V for a C-Si₀ 2-SiC nanocable device having a channel length of 2.7 gm.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 11 shows an embodiment of a repetitive bias voltage sweep of a C- SiO 2-SiC nanocable electronic device.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 20 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various C-Si O 2-Si nanocable electronic devices.
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 22 shows an embodiment of BIV behavior over a bias sweep range of -8 V to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.7 pm.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 24 shows an embodiment of a five-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.4 m.
Figure 25 shows an embodiment of a three-cycle bias sweep sequence from 0 to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 27 shows an embodiment of a two-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.9 p m and a nanocable diameter of 110 nm.
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 29 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 nm.
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 31 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.5 p m and a nanocable diameter of 200 nm.
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 34 shows an embodiment of the BIV behavior for a first C-SiO₂ nanocable device whose memory performance is shown in
Figure 35 shows an embodiment of the BIV behavior for a second C-Si O 2 nanocable device whose memory performance is shown in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 39 shows an embodiment of a proposed NEM switching mechanism responsible for BIV behavior in graphenic or graphitic nanocable electronic devices.
Figure 40 shows embodiments of BIV behavior for a C-Si O 2 nanocable electronic device over a temperature range between 200 K and 400 K.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
Figure 42 shows an embodiment of BIV behavior over a bias sweep range of 0 V to +15 V for the two-terminal electronic device presented in
Figure 43 shows an embodiment of the memory reading performance for the two- terminal electronic device presented in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device comprising: a dielectric material; two electrode terminals, wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain; at least one-earben two independent carbon sheets forming a discontinuous carbon layer disposed between the two electrode terminals, wherein the discontinuous carbon layer is deposited on the dielectric material, said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof, and the electronic device exhibits a nonlinear cu rr ent-versus-voltage response when operated over a voltage sweep range; and a channel length between the two electrode terminals, wherein the channel length is less than 1 p m, and the nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in current over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the at least one carbon shee selete d f rom a g roup conisiting O f g ra-phene, gra- phit e, a nid comfbin ati ons th ereof.
Page 2 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 4. The electronic device of claim 1, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device of claim 1 further comprising: a semiconductor; and wherein the dielectric material maintains continuous contact with the semiconductor.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited at a temperature between about 400 0 C and about 900 0C.
Page 3 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 11. The electronic device of claim 1, wherein the at least one carbon sheet is deposited from a gas comp risin g at least one carbon-containing compound.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited by a process selected from a group consisting of ink-jet printing and solution-spin coating.
The electronic device of claim 1, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and Page 4 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device of claim 1, wherein the nonlinear cu rr ent- versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the electronic device is operated over a voltage sweep range of less than about 15 V.
Page 5 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 23. The electronic device of claim 1, wherein the electronic device comprises a two-terminal memory device having an ON/OFF memory state.
The electronic device of claim 1 further comprising: a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1 further comprising: a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1, wherein the electronic device is constructed on a planar silicon wafer.
The electronic device of claim 1 further comprising: at least one nanowire; and Page 6 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one nanowire lies between the source and the drain.
The electronic device of claim 1, wherein the dielectric material and the carbon sheets form a nanocable, wherein the nanocable comprises at least two layers of material.
The electronic device of claim 1, wherein the electronic device comprises a sensor.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is chemically functionalized with covalent bonds.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is modified through non-covalent bonding.
The electronic device of claim 1 or claim 30, wherein operation of the electronic device within the voltage sweep range promotes displacement of at least one molecule from the at least one carbon sheet.
The electronic device of any one of claims 1, 25 or 26 wherein the electronic device comprises a logic switch.
An analytical method comprising: providing the electronic device of claim 1; operating the electronic device over a voltage sweep range; Page 8 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the operating step occurs in the presence of at least one analyte; and observing current-versus-voltage performance of the electronic device in the presence of the at least one analyte.
2.
17.
(Cu rr ently Amended) An electronic device prepared by a process compris ing: providing a dielectric material; depositing at least one-earbe two independent carbon sheets on the dielectric materia l, wherein said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof,; Page 9 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one--earbe two independent carbon sheets f erm s form a discontinuous carbon layer; and positioning two electrode terminals on the dielectric material; wherein the at least one-earben two inde p endent carbon sheets lie s lie between the two electrode terminals to form a channel, and a channel length between the two electrode terminals is less than 1 pm; wherein the electronic device provides a nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in cu rr ent over a voltage sweep range of about 0.5 V; and wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain.
The electronic device prepared by the process of claim 44 further comprising: applying a voltage sweep between the two electrode terminals; and wherein the voltage sweep produces a nonlinear current-versus-voltage response.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is selected from a group consisting of graphene and graphite.
Page 10 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 48. The electronic device prepared by the process of claim 44, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device prepared by the process of claim 44, wherein the dielectric material maintains continuous contact with a semiconductor.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed with a gas compris in g at least one carbon-containing compound.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed by ink-jet printing.
Page 11 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 54. The electronic device prepared by the process of claim 44, wherein the depositing step is performed by solution-spin coating.
The electronic device prepared by the process of claim 44, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device prepared by the process of claim 44, wherein the nonlinear cu rr ent-versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device prepared by the process of claim 44 further comp rising: Page 12 HOUSTON 1\1 248748v2 11321-P l65 US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US placing a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: placing a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: chemically functionalizing the at least one carbon sheet with covalent bonds.
The electronic device prepared by the process of claim 44 further comp rising: chemically modifying the at least one carbon sheet with non-covalent bonds.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is formed in situ on the dielectric material.
45.
56.
Layer stacks claimed or described, ordered top of device to substrate.
two-terminal electronic device with discontinuous carbon layer on dielectric
two-terminal memory device
No layer stack recorded.
nanocable device
Materials described outside the worked examples.
graphene
graphite
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | ≥10 fold | graphenegraphite |
Fet On Off Ratio |
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Patent
Atlas literature
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US 8,440,467Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an embodiment of C-Si O 2-SiC, C- Si₀ 2-Si, and C-Si O 2 nanocables.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Figure 3 shows a selected-area electron diffraction pattern of a C- Si₀ 2-SiC nanocable embodiment.
Figure 4 shows a n embodiment of a two-terminal electronic device and exemplary process steps for preparing the device.
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 7 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various long channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 8 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various short channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 9 shows an embodiment of a reverse bias sweep of +15 V to -15 V for a C-Si₀ 2-SiC nanocable device having a channel length of 2.7 gm.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 11 shows an embodiment of a repetitive bias voltage sweep of a C- SiO 2-SiC nanocable electronic device.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 20 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various C-Si O 2-Si nanocable electronic devices.
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 22 shows an embodiment of BIV behavior over a bias sweep range of -8 V to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.7 pm.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 24 shows an embodiment of a five-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.4 m.
Figure 25 shows an embodiment of a three-cycle bias sweep sequence from 0 to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 27 shows an embodiment of a two-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.9 p m and a nanocable diameter of 110 nm.
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 29 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 nm.
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 31 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.5 p m and a nanocable diameter of 200 nm.
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 34 shows an embodiment of the BIV behavior for a first C-SiO₂ nanocable device whose memory performance is shown in
Figure 35 shows an embodiment of the BIV behavior for a second C-Si O 2 nanocable device whose memory performance is shown in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 39 shows an embodiment of a proposed NEM switching mechanism responsible for BIV behavior in graphenic or graphitic nanocable electronic devices.
Figure 40 shows embodiments of BIV behavior for a C-Si O 2 nanocable electronic device over a temperature range between 200 K and 400 K.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
Figure 42 shows an embodiment of BIV behavior over a bias sweep range of 0 V to +15 V for the two-terminal electronic device presented in
Figure 43 shows an embodiment of the memory reading performance for the two- terminal electronic device presented in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device comprising: a dielectric material; two electrode terminals, wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain; at least one-earben two independent carbon sheets forming a discontinuous carbon layer disposed between the two electrode terminals, wherein the discontinuous carbon layer is deposited on the dielectric material, said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof, and the electronic device exhibits a nonlinear cu rr ent-versus-voltage response when operated over a voltage sweep range; and a channel length between the two electrode terminals, wherein the channel length is less than 1 p m, and the nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in current over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the at least one carbon shee selete d f rom a g roup conisiting O f g ra-phene, gra- phit e, a nid comfbin ati ons th ereof.
Page 2 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 4. The electronic device of claim 1, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device of claim 1 further comprising: a semiconductor; and wherein the dielectric material maintains continuous contact with the semiconductor.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited at a temperature between about 400 0 C and about 900 0C.
Page 3 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 11. The electronic device of claim 1, wherein the at least one carbon sheet is deposited from a gas comp risin g at least one carbon-containing compound.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited by a process selected from a group consisting of ink-jet printing and solution-spin coating.
The electronic device of claim 1, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and Page 4 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device of claim 1, wherein the nonlinear cu rr ent- versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the electronic device is operated over a voltage sweep range of less than about 15 V.
Page 5 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 23. The electronic device of claim 1, wherein the electronic device comprises a two-terminal memory device having an ON/OFF memory state.
The electronic device of claim 1 further comprising: a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1 further comprising: a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1, wherein the electronic device is constructed on a planar silicon wafer.
The electronic device of claim 1 further comprising: at least one nanowire; and Page 6 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one nanowire lies between the source and the drain.
The electronic device of claim 1, wherein the dielectric material and the carbon sheets form a nanocable, wherein the nanocable comprises at least two layers of material.
The electronic device of claim 1, wherein the electronic device comprises a sensor.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is chemically functionalized with covalent bonds.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is modified through non-covalent bonding.
The electronic device of claim 1 or claim 30, wherein operation of the electronic device within the voltage sweep range promotes displacement of at least one molecule from the at least one carbon sheet.
The electronic device of any one of claims 1, 25 or 26 wherein the electronic device comprises a logic switch.
An analytical method comprising: providing the electronic device of claim 1; operating the electronic device over a voltage sweep range; Page 8 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the operating step occurs in the presence of at least one analyte; and observing current-versus-voltage performance of the electronic device in the presence of the at least one analyte.
2.
17.
(Cu rr ently Amended) An electronic device prepared by a process compris ing: providing a dielectric material; depositing at least one-earbe two independent carbon sheets on the dielectric materia l, wherein said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof,; Page 9 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one--earbe two independent carbon sheets f erm s form a discontinuous carbon layer; and positioning two electrode terminals on the dielectric material; wherein the at least one-earben two inde p endent carbon sheets lie s lie between the two electrode terminals to form a channel, and a channel length between the two electrode terminals is less than 1 pm; wherein the electronic device provides a nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in cu rr ent over a voltage sweep range of about 0.5 V; and wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain.
The electronic device prepared by the process of claim 44 further comprising: applying a voltage sweep between the two electrode terminals; and wherein the voltage sweep produces a nonlinear current-versus-voltage response.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is selected from a group consisting of graphene and graphite.
Page 10 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 48. The electronic device prepared by the process of claim 44, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device prepared by the process of claim 44, wherein the dielectric material maintains continuous contact with a semiconductor.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed with a gas compris in g at least one carbon-containing compound.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed by ink-jet printing.
Page 11 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 54. The electronic device prepared by the process of claim 44, wherein the depositing step is performed by solution-spin coating.
The electronic device prepared by the process of claim 44, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device prepared by the process of claim 44, wherein the nonlinear cu rr ent-versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device prepared by the process of claim 44 further comp rising: Page 12 HOUSTON 1\1 248748v2 11321-P l65 US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US placing a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: placing a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: chemically functionalizing the at least one carbon sheet with covalent bonds.
The electronic device prepared by the process of claim 44 further comp rising: chemically modifying the at least one carbon sheet with non-covalent bonds.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is formed in situ on the dielectric material.
45.
56.
Layer stacks claimed or described, ordered top of device to substrate.
two-terminal electronic device with discontinuous carbon layer on dielectric
two-terminal memory device
No layer stack recorded.
nanocable device
Materials described outside the worked examples.
graphene
graphite
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | ≥10 fold | graphenegraphite |
Fet On Off Ratio |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 8,440,467Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an embodiment of C-Si O 2-SiC, C- Si₀ 2-Si, and C-Si O 2 nanocables.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Figure 3 shows a selected-area electron diffraction pattern of a C- Si₀ 2-SiC nanocable embodiment.
Figure 4 shows a n embodiment of a two-terminal electronic device and exemplary process steps for preparing the device.
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 7 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various long channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 8 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various short channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 9 shows an embodiment of a reverse bias sweep of +15 V to -15 V for a C-Si₀ 2-SiC nanocable device having a channel length of 2.7 gm.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 11 shows an embodiment of a repetitive bias voltage sweep of a C- SiO 2-SiC nanocable electronic device.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 20 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various C-Si O 2-Si nanocable electronic devices.
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 22 shows an embodiment of BIV behavior over a bias sweep range of -8 V to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.7 pm.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 24 shows an embodiment of a five-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.4 m.
Figure 25 shows an embodiment of a three-cycle bias sweep sequence from 0 to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 27 shows an embodiment of a two-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.9 p m and a nanocable diameter of 110 nm.
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 29 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 nm.
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 31 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.5 p m and a nanocable diameter of 200 nm.
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 34 shows an embodiment of the BIV behavior for a first C-SiO₂ nanocable device whose memory performance is shown in
Figure 35 shows an embodiment of the BIV behavior for a second C-Si O 2 nanocable device whose memory performance is shown in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 39 shows an embodiment of a proposed NEM switching mechanism responsible for BIV behavior in graphenic or graphitic nanocable electronic devices.
Figure 40 shows embodiments of BIV behavior for a C-Si O 2 nanocable electronic device over a temperature range between 200 K and 400 K.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
Figure 42 shows an embodiment of BIV behavior over a bias sweep range of 0 V to +15 V for the two-terminal electronic device presented in
Figure 43 shows an embodiment of the memory reading performance for the two- terminal electronic device presented in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device comprising: a dielectric material; two electrode terminals, wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain; at least one-earben two independent carbon sheets forming a discontinuous carbon layer disposed between the two electrode terminals, wherein the discontinuous carbon layer is deposited on the dielectric material, said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof, and the electronic device exhibits a nonlinear cu rr ent-versus-voltage response when operated over a voltage sweep range; and a channel length between the two electrode terminals, wherein the channel length is less than 1 p m, and the nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in current over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the at least one carbon shee selete d f rom a g roup conisiting O f g ra-phene, gra- phit e, a nid comfbin ati ons th ereof.
Page 2 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 4. The electronic device of claim 1, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device of claim 1 further comprising: a semiconductor; and wherein the dielectric material maintains continuous contact with the semiconductor.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited at a temperature between about 400 0 C and about 900 0C.
Page 3 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 11. The electronic device of claim 1, wherein the at least one carbon sheet is deposited from a gas comp risin g at least one carbon-containing compound.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited by a process selected from a group consisting of ink-jet printing and solution-spin coating.
The electronic device of claim 1, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and Page 4 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device of claim 1, wherein the nonlinear cu rr ent- versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the electronic device is operated over a voltage sweep range of less than about 15 V.
Page 5 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 23. The electronic device of claim 1, wherein the electronic device comprises a two-terminal memory device having an ON/OFF memory state.
The electronic device of claim 1 further comprising: a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1 further comprising: a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1, wherein the electronic device is constructed on a planar silicon wafer.
The electronic device of claim 1 further comprising: at least one nanowire; and Page 6 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one nanowire lies between the source and the drain.
The electronic device of claim 1, wherein the dielectric material and the carbon sheets form a nanocable, wherein the nanocable comprises at least two layers of material.
The electronic device of claim 1, wherein the electronic device comprises a sensor.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is chemically functionalized with covalent bonds.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is modified through non-covalent bonding.
The electronic device of claim 1 or claim 30, wherein operation of the electronic device within the voltage sweep range promotes displacement of at least one molecule from the at least one carbon sheet.
The electronic device of any one of claims 1, 25 or 26 wherein the electronic device comprises a logic switch.
An analytical method comprising: providing the electronic device of claim 1; operating the electronic device over a voltage sweep range; Page 8 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the operating step occurs in the presence of at least one analyte; and observing current-versus-voltage performance of the electronic device in the presence of the at least one analyte.
2.
17.
(Cu rr ently Amended) An electronic device prepared by a process compris ing: providing a dielectric material; depositing at least one-earbe two independent carbon sheets on the dielectric materia l, wherein said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof,; Page 9 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one--earbe two independent carbon sheets f erm s form a discontinuous carbon layer; and positioning two electrode terminals on the dielectric material; wherein the at least one-earben two inde p endent carbon sheets lie s lie between the two electrode terminals to form a channel, and a channel length between the two electrode terminals is less than 1 pm; wherein the electronic device provides a nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in cu rr ent over a voltage sweep range of about 0.5 V; and wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain.
The electronic device prepared by the process of claim 44 further comprising: applying a voltage sweep between the two electrode terminals; and wherein the voltage sweep produces a nonlinear current-versus-voltage response.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is selected from a group consisting of graphene and graphite.
Page 10 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 48. The electronic device prepared by the process of claim 44, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device prepared by the process of claim 44, wherein the dielectric material maintains continuous contact with a semiconductor.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed with a gas compris in g at least one carbon-containing compound.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed by ink-jet printing.
Page 11 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 54. The electronic device prepared by the process of claim 44, wherein the depositing step is performed by solution-spin coating.
The electronic device prepared by the process of claim 44, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device prepared by the process of claim 44, wherein the nonlinear cu rr ent-versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device prepared by the process of claim 44 further comp rising: Page 12 HOUSTON 1\1 248748v2 11321-P l65 US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US placing a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: placing a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: chemically functionalizing the at least one carbon sheet with covalent bonds.
The electronic device prepared by the process of claim 44 further comp rising: chemically modifying the at least one carbon sheet with non-covalent bonds.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is formed in situ on the dielectric material.
45.
56.
Layer stacks claimed or described, ordered top of device to substrate.
two-terminal electronic device with discontinuous carbon layer on dielectric
two-terminal memory device
No layer stack recorded.
nanocable device
Materials described outside the worked examples.
graphene
graphite
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | ≥10 fold | graphenegraphite |
Fet On Off Ratio |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 8,440,467Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an embodiment of C-Si O 2-SiC, C- Si₀ 2-Si, and C-Si O 2 nanocables.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Figure 3 shows a selected-area electron diffraction pattern of a C- Si₀ 2-SiC nanocable embodiment.
Figure 4 shows a n embodiment of a two-terminal electronic device and exemplary process steps for preparing the device.
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 7 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various long channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 8 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various short channel C- Si₀ 2-SiC nanocable electronic devices.
Figure 9 shows an embodiment of a reverse bias sweep of +15 V to -15 V for a C-Si₀ 2-SiC nanocable device having a channel length of 2.7 gm.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 11 shows an embodiment of a repetitive bias voltage sweep of a C- SiO 2-SiC nanocable electronic device.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 20 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various C-Si O 2-Si nanocable electronic devices.
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 22 shows an embodiment of BIV behavior over a bias sweep range of -8 V to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.7 pm.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 24 shows an embodiment of a five-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.4 m.
Figure 25 shows an embodiment of a three-cycle bias sweep sequence from 0 to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 27 shows an embodiment of a two-cycle bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.9 p m and a nanocable diameter of 110 nm.
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 29 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 nm.
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 31 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-Si O 2 nanocable electronic device having a channel length of 1.5 p m and a nanocable diameter of 200 nm.
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 34 shows an embodiment of the BIV behavior for a first C-SiO₂ nanocable device whose memory performance is shown in
Figure 35 shows an embodiment of the BIV behavior for a second C-Si O 2 nanocable device whose memory performance is shown in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 39 shows an embodiment of a proposed NEM switching mechanism responsible for BIV behavior in graphenic or graphitic nanocable electronic devices.
Figure 40 shows embodiments of BIV behavior for a C-Si O 2 nanocable electronic device over a temperature range between 200 K and 400 K.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
Figure 42 shows an embodiment of BIV behavior over a bias sweep range of 0 V to +15 V for the two-terminal electronic device presented in
Figure 43 shows an embodiment of the memory reading performance for the two- terminal electronic device presented in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) An electronic device comprising: a dielectric material; two electrode terminals, wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain; at least one-earben two independent carbon sheets forming a discontinuous carbon layer disposed between the two electrode terminals, wherein the discontinuous carbon layer is deposited on the dielectric material, said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof, and the electronic device exhibits a nonlinear cu rr ent-versus-voltage response when operated over a voltage sweep range; and a channel length between the two electrode terminals, wherein the channel length is less than 1 p m, and the nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in current over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the at least one carbon shee selete d f rom a g roup conisiting O f g ra-phene, gra- phit e, a nid comfbin ati ons th ereof.
Page 2 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 4. The electronic device of claim 1, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device of claim 1 further comprising: a semiconductor; and wherein the dielectric material maintains continuous contact with the semiconductor.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited at a temperature between about 400 0 C and about 900 0C.
Page 3 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 11. The electronic device of claim 1, wherein the at least one carbon sheet is deposited from a gas comp risin g at least one carbon-containing compound.
The electronic device of claim 1, wherein the at least one carbon sheet is deposited by a process selected from a group consisting of ink-jet printing and solution-spin coating.
The electronic device of claim 1, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and Page 4 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device of claim 1, wherein the nonlinear cu rr ent- versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device of claim 1, wherein the electronic device is operated over a voltage sweep range of less than about 15 V.
Page 5 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 23. The electronic device of claim 1, wherein the electronic device comprises a two-terminal memory device having an ON/OFF memory state.
The electronic device of claim 1 further comprising: a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1 further comprising: a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device of claim 1, wherein the electronic device is constructed on a planar silicon wafer.
The electronic device of claim 1 further comprising: at least one nanowire; and Page 6 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one nanowire lies between the source and the drain.
The electronic device of claim 1, wherein the dielectric material and the carbon sheets form a nanocable, wherein the nanocable comprises at least two layers of material.
The electronic device of claim 1, wherein the electronic device comprises a sensor.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is chemically functionalized with covalent bonds.
The electronic device of claim 1 or claim 30, wherein the at least one carbon sheet is modified through non-covalent bonding.
The electronic device of claim 1 or claim 30, wherein operation of the electronic device within the voltage sweep range promotes displacement of at least one molecule from the at least one carbon sheet.
The electronic device of any one of claims 1, 25 or 26 wherein the electronic device comprises a logic switch.
An analytical method comprising: providing the electronic device of claim 1; operating the electronic device over a voltage sweep range; Page 8 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the operating step occurs in the presence of at least one analyte; and observing current-versus-voltage performance of the electronic device in the presence of the at least one analyte.
2.
17.
(Cu rr ently Amended) An electronic device prepared by a process compris ing: providing a dielectric material; depositing at least one-earbe two independent carbon sheets on the dielectric materia l, wherein said at least two independent carbon sheets are selected from a group consisting of graphene, graphite, and combinations thereof,; Page 9 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US wherein the at least one--earbe two independent carbon sheets f erm s form a discontinuous carbon layer; and positioning two electrode terminals on the dielectric material; wherein the at least one-earben two inde p endent carbon sheets lie s lie between the two electrode terminals to form a channel, and a channel length between the two electrode terminals is less than 1 pm; wherein the electronic device provides a nonlinear cu rr ent-versus-voltage response comprises at least about a 10-fold change in cu rr ent over a voltage sweep range of about 0.5 V; and wherein a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain.
The electronic device prepared by the process of claim 44 further comprising: applying a voltage sweep between the two electrode terminals; and wherein the voltage sweep produces a nonlinear current-versus-voltage response.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is selected from a group consisting of graphene and graphite.
Page 10 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 48. The electronic device prepared by the process of claim 44, wherein the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
The electronic device prepared by the process of claim 44, wherein the dielectric material maintains continuous contact with a semiconductor.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed with a gas compris in g at least one carbon-containing compound.
The electronic device prepared by the process of claim 44, wherein the depositing step is performed by ink-jet printing.
Page 11 HOUSTON 1\1 248748v2 11321-P l 65US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US 54. The electronic device prepared by the process of claim 44, wherein the depositing step is performed by solution-spin coating.
The electronic device prepared by the process of claim 44, wherein the source and the drain are constructed from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof; and the selections of the at least one material for the source and for the drain are conducted independently.
The electronic device prepared by the process of claim 44, wherein the nonlinear cu rr ent-versus-voltage response comprises a change in current between about 10-fold and 109-fold over a voltage sweep range of about 0.5 V.
The electronic device prepared by the process of claim 44 further comp rising: Page 12 HOUSTON 1\1 248748v2 11321-P l65 US 12/03/2012 Serial No. 12/240,673 Atty Dkt No. 11321-P 1 65US placing a gate electrode above the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: placing a gate electrode below the at least one carbon sheet; and wherein the gate electrode modifies cu rr ent flow through the at least one carbon sheet.
The electronic device prepared by the process of claim 44 further comp rising: chemically functionalizing the at least one carbon sheet with covalent bonds.
The electronic device prepared by the process of claim 44 further comp rising: chemically modifying the at least one carbon sheet with non-covalent bonds.
The electronic device prepared by the process of claim 44, wherein the at least one carbon sheet is formed in situ on the dielectric material.
45.
56.
Layer stacks claimed or described, ordered top of device to substrate.
two-terminal electronic device with discontinuous carbon layer on dielectric
two-terminal memory device
No layer stack recorded.
nanocable device
Materials described outside the worked examples.
graphene
graphite
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows a high-resolution TEM image of a C-Si O 2-SiC nanocable embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | ≥10 fold | graphenegraphite |
Fet On Off Ratio |
Related documents with shared materials, methods, properties, or citations.
sensor device
No layer stack recorded.
logic switch
No layer stack recorded.
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
glass
plastic
silicon
Si
silicon carbide
SiC
gallium arsenide
GaAs
germanium
Ge
acetylene
C₂H₂
ethylene
C₂H₄
methane
CH₄
ethane
C₂H₆
carbon monoxide
CO
platinum
Pt
palladium
Pd
gold
Au
silver
Ag
titanium
Ti
tin
Sn
copper
Cu
C-SiO₂-SiC nanocable
C-SiO₂-Si nanocable
C-SiO₂ nanocable
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
graphenegraphite |
Thickness | 20–50 nm | — |
Thickness | 2–5 nm | — |
Voltage | 0–10 V | — |
Voltage | 0–8 V | — |
Voltage | 3.24–6.76 V | — |
Voltage | 6–12 V | — |
Voltage | 3.8–7.1 V | — |
Thickness | 50–120 nm | — |
Temperature | 250–400 K | — |
Voltage | ≤ 5 V | — |
Voltage | ≤ 15 V | — |
Voltage | ≤ 1 V | — |
Pressure | ≤ 10 pA | — |
Voltage | ≤ 3.6 V | — |
sensor device
No layer stack recorded.
logic switch
No layer stack recorded.
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
glass
plastic
silicon
Si
silicon carbide
SiC
gallium arsenide
GaAs
germanium
Ge
acetylene
C₂H₂
ethylene
C₂H₄
methane
CH₄
ethane
C₂H₆
carbon monoxide
CO
platinum
Pt
palladium
Pd
gold
Au
silver
Ag
titanium
Ti
tin
Sn
copper
Cu
C-SiO₂-SiC nanocable
C-SiO₂-Si nanocable
C-SiO₂ nanocable
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
graphenegraphite |
Thickness | 20–50 nm | — |
Thickness | 2–5 nm | — |
Voltage | 0–10 V | — |
Voltage | 0–8 V | — |
Voltage | 3.24–6.76 V | — |
Voltage | 6–12 V | — |
Voltage | 3.8–7.1 V | — |
Thickness | 50–120 nm | — |
Temperature | 250–400 K | — |
Voltage | ≤ 5 V | — |
Voltage | ≤ 15 V | — |
Voltage | ≤ 1 V | — |
Pressure | ≤ 10 pA | — |
Voltage | ≤ 3.6 V | — |
sensor device
No layer stack recorded.
logic switch
No layer stack recorded.
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
glass
plastic
silicon
Si
silicon carbide
SiC
gallium arsenide
GaAs
germanium
Ge
acetylene
C₂H₂
ethylene
C₂H₄
methane
CH₄
ethane
C₂H₆
carbon monoxide
CO
platinum
Pt
palladium
Pd
gold
Au
silver
Ag
titanium
Ti
tin
Sn
copper
Cu
C-SiO₂-SiC nanocable
C-SiO₂-Si nanocable
C-SiO₂ nanocable
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
graphenegraphite |
Thickness | 20–50 nm | — |
Thickness | 2–5 nm | — |
Voltage | 0–10 V | — |
Voltage | 0–8 V | — |
Voltage | 3.24–6.76 V | — |
Voltage | 6–12 V | — |
Voltage | 3.8–7.1 V | — |
Thickness | 50–120 nm | — |
Temperature | 250–400 K | — |
Voltage | ≤ 5 V | — |
Voltage | ≤ 15 V | — |
Voltage | ≤ 1 V | — |
Pressure | ≤ 10 pA | — |
Voltage | ≤ 3.6 V | — |
sensor device
No layer stack recorded.
logic switch
No layer stack recorded.
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
glass
plastic
silicon
Si
silicon carbide
SiC
gallium arsenide
GaAs
germanium
Ge
acetylene
C₂H₂
ethylene
C₂H₄
methane
CH₄
ethane
C₂H₆
carbon monoxide
CO
platinum
Pt
palladium
Pd
gold
Au
silver
Ag
titanium
Ti
tin
Sn
copper
Cu
C-SiO₂-SiC nanocable
C-SiO₂-Si nanocable
C-SiO₂ nanocable
Figure 5 shows a representative embodiment of an SEM image of a long channel C-Si₀ 2-SiC nanocable electronic device.
Figure 6 shows a representative embodiment of an SEM image of a short channel C-Si O 2-SiC nanocable electronic device.
Figure 10 shows an embodiment of variable temperature conductance of C- Si₀ 2-SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
Figure 12 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 2.8 g m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
Figure 13 shows an embodiment of the memory performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-Si O 2-SiC nanocable electronic device having a channel length of 4.5 p m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at …
Figure 15 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads …
Figure 17 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 18 shows an embodiment of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
Figure 19 shows embodiments of the memory reading performance of a short channel C-Si O 2-SiC nanocable electronic device having a channel length of 700 nm, as obtained from a 5 Attorney Docket No.: 11321/P₁₆₅US Patent Application +3 V write bias pulse and a +6 V erase bias pulse, with a …
Figure 21 shows an embodiment of the memory reading performance of a C-Si O 2-Si nanocable electronic device, as obtained from a + 4 V write bias pulse for 1 second and a + 8 V erase bias pulse for 1 second.
Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-Si O 2 nanocable electronic device having a channel length of 2.5 m, as conducted in the presence of -20, 0, and +20 V gate biases.
Figure 26 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.5 p m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 28 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.9 m and a nanocable diameter of 110 6 Attorney Docket No.: 11321/P₁₆₅US Patent Application nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase …
Figure 30 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 2.6 p m and a nanocable diameter of 140 n m, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being …
Figure 32 shows an embodiment of the memory reading performance of a C-Si O₂ nanocable electronic device having a channel length of 1.5 m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ps and a +8 V erase bias pulse for 100 gs, each write/erase operation being …
Figure 33 shows an embodiment of the memory reading performance of two C-Si O₂ nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 36 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices before and after the extended electrical property measurements presented in
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 38 shows embodiments of SEM images of C-Si O 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to
graphenegraphite |
Thickness | 20–50 nm | — |
Thickness | 2–5 nm | — |
Voltage | 0–10 V | — |
Voltage | 0–8 V | — |
Voltage | 3.24–6.76 V | — |
Voltage | 6–12 V | — |
Voltage | 3.8–7.1 V | — |
Thickness | 50–120 nm | — |
Temperature | 250–400 K | — |
Voltage | ≤ 5 V | — |
Voltage | ≤ 15 V | — |
Voltage | ≤ 1 V | — |
Pressure | ≤ 10 pA | — |
Voltage | ≤ 3.6 V | — |