A method of forming a transistor comprising: Forming a channel la y er including GaN; forming a barrier layer, the ba rri er layer including AlGaN; forming a lower transition la y er touching the barrier la yer forming a layer of Si₃N₄ that touches the ba mier lower transition layer on the lower side of the Si 3N4, wherein the Si N₄ la y er and the ba rri er la y er share anions to produce the lower transition la ver; an up per transition la y er touching the Si N₄ on the up per side of the Si 3N4, the up per transition la yer produced by an oxidation of the Si 3N4; forming a layer of SiO 2 that touches the upper transition layer and lying over the region of Si₃N4; a+d SVG 14091606.05-08-2014.HUYLOJZSPXXIFW3.CLM.1.svg 0.16 6 Black and white bottom surface that touches the top surface of the region of SiO 2 in a horizontal plane, and being spaced apart from the region of Si 3N4, no portion of the region of SiO, lying above the horizontal p lane, forming a spaced-apart metal source region and metal drain region that touch the ba rrier lav er, wherein the ba rri er la v er including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal -2- ATTORNEY DOCKET NO. PATENT APPLICATION TI-88120.1 SERIAL NO. 14/091,606 drain region are differently biased, substantially no electrons comprise a two-dimensional electron ga s region between the barrier la y er including AlGaN and the channel la y er including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal g ate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier la y er including A l GaN and the channel la v er including GaN, and the electrons flow from the metal source region to the metal drain re g ion.

A method of forming a transistor comprising: Forming a channel la y er including GaN; forming a barrier layer, the ba rri er layer including AlGaN; forming a lower transition la y er touching the barrier la yer forming a layer of Si₃N₄ that touches the ba mier lower transition layer on the lower side of the Si 3N4, wherein the Si N₄ la y er and the ba rri er la y er share anions to produce the lower transition la ver; an up per transition la y er touching the Si N₄ on the up per side of the Si 3N4, the up per transition la yer produced by an oxidation of the Si 3N4; forming a layer of SiO 2 that touches the upper transition layer and lying over the region of Si₃N4; a+d SVG 14091606.05-08-2014.HUYLOJZSPXXIFW3.CLM.1.svg 0.16 6 Black and white bottom surface that touches the top surface of the region of SiO 2 in a horizontal plane, and being spaced apart from the region of Si 3N4, no portion of the region of SiO, lying above the horizontal p lane, forming a spaced-apart metal source region and metal drain region that touch the ba rrier lav er, wherein the ba rri er la v er including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal -2- ATTORNEY DOCKET NO. PATENT APPLICATION TI-88120.1 SERIAL NO. 14/091,606 drain region are differently biased, substantially no electrons comprise a two-dimensional electron ga s region between the barrier la y er including AlGaN and the channel la y er including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal g ate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier la y er including A l GaN and the channel la v er including GaN, and the electrons flow from the metal source region to the metal drain re g ion.

A method of forming a transistor comprising: Forming a channel la y er including GaN; forming a barrier layer, the ba rri er layer including AlGaN; forming a lower transition la y er touching the barrier la yer forming a layer of Si₃N₄ that touches the ba mier lower transition layer on the lower side of the Si 3N4, wherein the Si N₄ la y er and the ba rri er la y er share anions to produce the lower transition la ver; an up per transition la y er touching the Si N₄ on the up per side of the Si 3N4, the up per transition la yer produced by an oxidation of the Si 3N4; forming a layer of SiO 2 that touches the upper transition layer and lying over the region of Si₃N4; a+d SVG 14091606.05-08-2014.HUYLOJZSPXXIFW3.CLM.1.svg 0.16 6 Black and white bottom surface that touches the top surface of the region of SiO 2 in a horizontal plane, and being spaced apart from the region of Si 3N4, no portion of the region of SiO, lying above the horizontal p lane, forming a spaced-apart metal source region and metal drain region that touch the ba rrier lav er, wherein the ba rri er la v er including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal -2- ATTORNEY DOCKET NO. PATENT APPLICATION TI-88120.1 SERIAL NO. 14/091,606 drain region are differently biased, substantially no electrons comprise a two-dimensional electron ga s region between the barrier la y er including AlGaN and the channel la y er including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal g ate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier la y er including A l GaN and the channel la v er including GaN, and the electrons flow from the metal source region to the metal drain re g ion.

A method of forming a transistor comprising: Forming a channel la y er including GaN; forming a barrier layer, the ba rri er layer including AlGaN; forming a lower transition la y er touching the barrier la yer forming a layer of Si₃N₄ that touches the ba mier lower transition layer on the lower side of the Si 3N4, wherein the Si N₄ la y er and the ba rri er la y er share anions to produce the lower transition la ver; an up per transition la y er touching the Si N₄ on the up per side of the Si 3N4, the up per transition la yer produced by an oxidation of the Si 3N4; forming a layer of SiO 2 that touches the upper transition layer and lying over the region of Si₃N4; a+d SVG 14091606.05-08-2014.HUYLOJZSPXXIFW3.CLM.1.svg 0.16 6 Black and white bottom surface that touches the top surface of the region of SiO 2 in a horizontal plane, and being spaced apart from the region of Si 3N4, no portion of the region of SiO, lying above the horizontal p lane, forming a spaced-apart metal source region and metal drain region that touch the ba rrier lav er, wherein the ba rri er la v er including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal -2- ATTORNEY DOCKET NO. PATENT APPLICATION TI-88120.1 SERIAL NO. 14/091,606 drain region are differently biased, substantially no electrons comprise a two-dimensional electron ga s region between the barrier la y er including AlGaN and the channel la y er including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal g ate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier la y er including A l GaN and the channel la v er including GaN, and the electrons flow from the metal source region to the metal drain re g ion.