Patent
US 10,665,683GaN MATERIAL AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Fumimasa HORIKIRI
US
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US 10,665,683Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 2. Examples of such impurities include th ose serving to impart electr o conductivity to the substrate 10, and may be n-type impurities, for example. …
FIG. 3, a stack 30 (also referred to as an "epitaxial substrate 30" below), which includes a substrate 10 and a GaN layer 20 that is epitaxially grown (also …
FIG. 4 is a schematic structural diagram illustrating an example of an electrochemical cell 300 used in anodic oxidation etching. A container 310 stores an …
FIG. 5 illustrates the etching currents corresponding to cases where the etching voltages of 0 V, 1 V, 2 V, and 3 V were used. F o r all etching voltages, an …
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 9 is a graph in which the etching voltage of 1 V and the vicinity thereof in
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 14C illustrates activation annealing. Activation annealing is carried out to activate the n-type impurities in the epitaxial layer 21n, thereby making the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 p m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of I V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
The GaN material according to claim 1, wherein the GaN material is a GaN substrate.
The GaN material according to claim 1, wherein the GaN material has a GaN substrate and a GaN layer epitaxially grown on the GaN substrate.
The GaN material according to claim I, wherein a maximum in-plane dislocation density is less than 1 x 10 7/cm 2, which is the plane where the recess of the GaN material is formed.
A method of manufacturing a semiconductor device, comprising: performing anodic oxidation etching to a region where a dislocation density of GaN material is less than 1 X 107/cm 2 by applying an etching voltage while irradiating this region with UV light, to form a recess, wherein the etching voltage is the voltage preferably in a range of 0.16 V or more and 1.30 V or less, more preferably in a range of 0.52 V or more and 1.15 V or less.
The method of manufacturing a semiconductor device according to claim 8, wherein in forming the recess, the irradiation of the UV light and the application of the etching voltage are intermittently repeated.
1 1. A method of manufacturing a semiconductor device, comprising: preparing a GaN material having a GaN substrate and a GaN layer epitaxially grown on the GaN substrate, the epitaxially grown GaN layer further including a GaN layer doped with p-type impurities and not annealed to activate the p-type impurities; and performing anodic oxidation etching to the GaN layer while irradiating the GaN material with UV light, thereby performing etching to the GaN layer doped with p-type impurities and not annealed to activate the p-type impurities, to form a recess.
The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxially grown GaN layer f u rther has a GaN layer doped with n-type impurities, and by etching the GaN layer doped with n-type impurities in the anodic oxidation etching, the recess is formed so as to expose a side surface of an epitaxially grown pn junction.
The method of manufacturing a semiconductor device according to claim 11, comprising a step of annealing to activate the p-type impurities after the anodic oxidation etching.
Materials described outside the worked examples.
GaN material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
arithmetic mean line roughness Ra at bottom surface of recess | ≤ 15 nm | GaN |
maximum in-plane dislocation density in recess plane | ≤ 10000000 /cm2 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,665,683Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 2. Examples of such impurities include th ose serving to impart electr o conductivity to the substrate 10, and may be n-type impurities, for example. …
FIG. 3, a stack 30 (also referred to as an "epitaxial substrate 30" below), which includes a substrate 10 and a GaN layer 20 that is epitaxially grown (also …
FIG. 4 is a schematic structural diagram illustrating an example of an electrochemical cell 300 used in anodic oxidation etching. A container 310 stores an …
FIG. 5 illustrates the etching currents corresponding to cases where the etching voltages of 0 V, 1 V, 2 V, and 3 V were used. F o r all etching voltages, an …
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 9 is a graph in which the etching voltage of 1 V and the vicinity thereof in
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 14C illustrates activation annealing. Activation annealing is carried out to activate the n-type impurities in the epitaxial layer 21n, thereby making the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 p m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of I V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
The GaN material according to claim 1, wherein the GaN material is a GaN substrate.
The GaN material according to claim 1, wherein the GaN material has a GaN substrate and a GaN layer epitaxially grown on the GaN substrate.
The GaN material according to claim I, wherein a maximum in-plane dislocation density is less than 1 x 10 7/cm 2, which is the plane where the recess of the GaN material is formed.
A method of manufacturing a semiconductor device, comprising: performing anodic oxidation etching to a region where a dislocation density of GaN material is less than 1 X 107/cm 2 by applying an etching voltage while irradiating this region with UV light, to form a recess, wherein the etching voltage is the voltage preferably in a range of 0.16 V or more and 1.30 V or less, more preferably in a range of 0.52 V or more and 1.15 V or less.
The method of manufacturing a semiconductor device according to claim 8, wherein in forming the recess, the irradiation of the UV light and the application of the etching voltage are intermittently repeated.
1 1. A method of manufacturing a semiconductor device, comprising: preparing a GaN material having a GaN substrate and a GaN layer epitaxially grown on the GaN substrate, the epitaxially grown GaN layer further including a GaN layer doped with p-type impurities and not annealed to activate the p-type impurities; and performing anodic oxidation etching to the GaN layer while irradiating the GaN material with UV light, thereby performing etching to the GaN layer doped with p-type impurities and not annealed to activate the p-type impurities, to form a recess.
The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxially grown GaN layer f u rther has a GaN layer doped with n-type impurities, and by etching the GaN layer doped with n-type impurities in the anodic oxidation etching, the recess is formed so as to expose a side surface of an epitaxially grown pn junction.
The method of manufacturing a semiconductor device according to claim 11, comprising a step of annealing to activate the p-type impurities after the anodic oxidation etching.
Materials described outside the worked examples.
GaN material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
arithmetic mean line roughness Ra at bottom surface of recess | ≤ 15 nm | GaN |
maximum in-plane dislocation density in recess plane | ≤ 10000000 /cm2 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,665,683Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 2. Examples of such impurities include th ose serving to impart electr o conductivity to the substrate 10, and may be n-type impurities, for example. …
FIG. 3, a stack 30 (also referred to as an "epitaxial substrate 30" below), which includes a substrate 10 and a GaN layer 20 that is epitaxially grown (also …
FIG. 4 is a schematic structural diagram illustrating an example of an electrochemical cell 300 used in anodic oxidation etching. A container 310 stores an …
FIG. 5 illustrates the etching currents corresponding to cases where the etching voltages of 0 V, 1 V, 2 V, and 3 V were used. F o r all etching voltages, an …
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 9 is a graph in which the etching voltage of 1 V and the vicinity thereof in
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 14C illustrates activation annealing. Activation annealing is carried out to activate the n-type impurities in the epitaxial layer 21n, thereby making the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 p m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of I V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
The GaN material according to claim 1, wherein the GaN material is a GaN substrate.
The GaN material according to claim 1, wherein the GaN material has a GaN substrate and a GaN layer epitaxially grown on the GaN substrate.
The GaN material according to claim I, wherein a maximum in-plane dislocation density is less than 1 x 10 7/cm 2, which is the plane where the recess of the GaN material is formed.
A method of manufacturing a semiconductor device, comprising: performing anodic oxidation etching to a region where a dislocation density of GaN material is less than 1 X 107/cm 2 by applying an etching voltage while irradiating this region with UV light, to form a recess, wherein the etching voltage is the voltage preferably in a range of 0.16 V or more and 1.30 V or less, more preferably in a range of 0.52 V or more and 1.15 V or less.
The method of manufacturing a semiconductor device according to claim 8, wherein in forming the recess, the irradiation of the UV light and the application of the etching voltage are intermittently repeated.
1 1. A method of manufacturing a semiconductor device, comprising: preparing a GaN material having a GaN substrate and a GaN layer epitaxially grown on the GaN substrate, the epitaxially grown GaN layer further including a GaN layer doped with p-type impurities and not annealed to activate the p-type impurities; and performing anodic oxidation etching to the GaN layer while irradiating the GaN material with UV light, thereby performing etching to the GaN layer doped with p-type impurities and not annealed to activate the p-type impurities, to form a recess.
The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxially grown GaN layer f u rther has a GaN layer doped with n-type impurities, and by etching the GaN layer doped with n-type impurities in the anodic oxidation etching, the recess is formed so as to expose a side surface of an epitaxially grown pn junction.
The method of manufacturing a semiconductor device according to claim 11, comprising a step of annealing to activate the p-type impurities after the anodic oxidation etching.
Materials described outside the worked examples.
GaN material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
arithmetic mean line roughness Ra at bottom surface of recess | ≤ 15 nm | GaN |
maximum in-plane dislocation density in recess plane | ≤ 10000000 /cm2 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,665,683Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 2. Examples of such impurities include th ose serving to impart electr o conductivity to the substrate 10, and may be n-type impurities, for example. …
FIG. 3, a stack 30 (also referred to as an "epitaxial substrate 30" below), which includes a substrate 10 and a GaN layer 20 that is epitaxially grown (also …
FIG. 4 is a schematic structural diagram illustrating an example of an electrochemical cell 300 used in anodic oxidation etching. A container 310 stores an …
FIG. 5 illustrates the etching currents corresponding to cases where the etching voltages of 0 V, 1 V, 2 V, and 3 V were used. F o r all etching voltages, an …
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 9 is a graph in which the etching voltage of 1 V and the vicinity thereof in
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 14C illustrates activation annealing. Activation annealing is carried out to activate the n-type impurities in the epitaxial layer 21n, thereby making the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN material having arithmetic mean line roughness Ra of 15 nm or less at a measurement length of 100 p m on a bottom surface of a recess when anodic oxidation etching is performed at an etching voltage of I V while irradiating the GaN material with UV light to form the recess of 2 m in depth.
The GaN material according to claim 1, wherein the GaN material is a GaN substrate.
The GaN material according to claim 1, wherein the GaN material has a GaN substrate and a GaN layer epitaxially grown on the GaN substrate.
The GaN material according to claim I, wherein a maximum in-plane dislocation density is less than 1 x 10 7/cm 2, which is the plane where the recess of the GaN material is formed.
A method of manufacturing a semiconductor device, comprising: performing anodic oxidation etching to a region where a dislocation density of GaN material is less than 1 X 107/cm 2 by applying an etching voltage while irradiating this region with UV light, to form a recess, wherein the etching voltage is the voltage preferably in a range of 0.16 V or more and 1.30 V or less, more preferably in a range of 0.52 V or more and 1.15 V or less.
The method of manufacturing a semiconductor device according to claim 8, wherein in forming the recess, the irradiation of the UV light and the application of the etching voltage are intermittently repeated.
1 1. A method of manufacturing a semiconductor device, comprising: preparing a GaN material having a GaN substrate and a GaN layer epitaxially grown on the GaN substrate, the epitaxially grown GaN layer further including a GaN layer doped with p-type impurities and not annealed to activate the p-type impurities; and performing anodic oxidation etching to the GaN layer while irradiating the GaN material with UV light, thereby performing etching to the GaN layer doped with p-type impurities and not annealed to activate the p-type impurities, to form a recess.
The method of manufacturing a semiconductor device according to claim 11, wherein the epitaxially grown GaN layer f u rther has a GaN layer doped with n-type impurities, and by etching the GaN layer doped with n-type impurities in the anodic oxidation etching, the recess is formed so as to expose a side surface of an epitaxially grown pn junction.
The method of manufacturing a semiconductor device according to claim 11, comprising a step of annealing to activate the p-type impurities after the anodic oxidation etching.
Materials described outside the worked examples.
GaN material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
arithmetic mean line roughness Ra at bottom surface of recess | ≤ 15 nm | GaN |
maximum in-plane dislocation density in recess plane | ≤ 10000000 /cm2 |
Related documents with shared materials, methods, properties, or citations.
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 1G. The crystal face with a l o w index closest to the principal face 10 s of the substrate 10 illustrated in
FIG. 6 is a graph illustrating a relationship between an amount of charge per unit area consumed by anodic o xidati o n and etched depth (etch depth, etching …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 7, the results obtained with the etching voltage of 1 V are illustrated in enlarged fashion as representative results, and together therewith, the results …
FIG. 8 is a graph illustrating a relationship between an etching voltage and profile roughness Ra in a case where the etched depth is 2 pm;
FIG. 10D i s a SEM image o bta ined in a case where no etching is c arr ied out. It can be seen th on the bottom surface of the recess has superior flatness f o …
FIGS. 12A through 12D are at om ic f o rce m icr osco pic (AFM) images of the botto m surfaces of the recesses f o rmed in the cases where the etching voltages …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …
FIG. 13 is a graph illustrating how the photoluminescence (PL) characteristics of a GaN material change according to anodic oxidation etching and illustrates …