Patent
US 10,249,491METHOD AND APPARATUS FOR FORMING DEVICE QUALITY GALLIUM NITRIDE LAYERS ON SILICON SUBSTRATES
Ganesh Sundaram
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,249,491Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface; applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method; applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an Al x Gai-x N compound and wherein each of the plurality of different Al xGai-x N compounds is applied by a different atomic layer deposition method; and applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method. Currently amended
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 800 °C. Original
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 400 °C. Original
The method of claim 1 wherein the silicon substrate comprises a single crystal, wherein the silicon substrate coating surface comprises a crystallographic plane, and wherein the step of applying the gallium nitride device layer over the transition layer creates a material interface characterized by both a coefficient of thermal expansion mismatch and a crystal lattice spacing mismatch, wherein one of the coefficient of thermal expansion mismatch or the crystal lattice spacing mismatch is smaller at the material interface than a coefficient of thermal expansion mismatch or a crystal lattice spacing mismatch at a material interface between gallium nitride deposited on the crystallographic plane of silicon. Original
The method of claim 1 further comprising heating one of the aluminum nitride nucleation layer, the transition layer, or the gallium nitride device layer to an annealing temperature above 900 ° C for less than 20 msec. Original
cancelled Canceled
The method of claim [[4]] 1 wherein each of the first, the second and the third atomic layer deposition methods and each of the different atomic layer deposition methods used is performed at the same atomic layer deposition reaction temperature. Currently amended
A solid state element formed by a method comprising: depositing, by a first atomic layer deposition method, a first material deposition layer over a coating surface of a silicon substrate; depositing, by a second atomic layer deposition method, a second material deposition layer over the first deposition layer, the second material composition being different than the first material composition; wherein each of the first and the second atomic layer deposition methods is performed at a reaction temperature of between 80 ° C and 800 ° C and each of the deposition layers is characterized by an as applied crystal lattice structure; and heating at least one of the first and second deposition layers to an annealing temperature above 900 ° C for less than 20 msec to alter the as applied crystal lattice of the heated deposition layer. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the first material deposition layer and a single crystal lattice spacing of the silicon substrate are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the second material deposition layer and a single crystal lattice spacing of the first material deposition layer are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein the composition of at least one of the first material deposition layer and the second material deposition layer comprises one of a group III -V, group I I-VI, or a group III -N material. Original
The solid state element of claim 17 wherein the second material deposition layer comprises one of silicon carbide, gallium nitride, or diamond. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride. Original
The solid state element of claim 17 wherein the first material deposition layer comprises yttrium oxide and the second material deposition layer comprises zinc oxide. Original
The solid state element of claim 17 wherein the method further comprises depositing a transition material deposition layer on the first material deposition layer before depositing the second material deposition layer, and wherein the transition material deposition layer comprises a plurality of different material layers each having a different material layer composition and each formed by a different atomic layer deposition process. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride and wherein the method further comprises depositing a boron nitride release layer over the first material deposition layer wherein the boron nitride release layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, depositing a second aluminum nitride layer over the boron nitride release layer wherein the second aluminum nitride layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, and wherein the second material deposition layer has a layer thickness of at least 2.5 m and a minimum breakdown voltage of 100 volts. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si heteroepitaxial stack
solid state element with ALD-deposited heteroepitaxial layers on silicon
Materials described outside the worked examples.
silicon substrate
Si
aluminum nitride nucleation layer
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 80–800 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,491Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface; applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method; applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an Al x Gai-x N compound and wherein each of the plurality of different Al xGai-x N compounds is applied by a different atomic layer deposition method; and applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method. Currently amended
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 800 °C. Original
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 400 °C. Original
The method of claim 1 wherein the silicon substrate comprises a single crystal, wherein the silicon substrate coating surface comprises a crystallographic plane, and wherein the step of applying the gallium nitride device layer over the transition layer creates a material interface characterized by both a coefficient of thermal expansion mismatch and a crystal lattice spacing mismatch, wherein one of the coefficient of thermal expansion mismatch or the crystal lattice spacing mismatch is smaller at the material interface than a coefficient of thermal expansion mismatch or a crystal lattice spacing mismatch at a material interface between gallium nitride deposited on the crystallographic plane of silicon. Original
The method of claim 1 further comprising heating one of the aluminum nitride nucleation layer, the transition layer, or the gallium nitride device layer to an annealing temperature above 900 ° C for less than 20 msec. Original
cancelled Canceled
The method of claim [[4]] 1 wherein each of the first, the second and the third atomic layer deposition methods and each of the different atomic layer deposition methods used is performed at the same atomic layer deposition reaction temperature. Currently amended
A solid state element formed by a method comprising: depositing, by a first atomic layer deposition method, a first material deposition layer over a coating surface of a silicon substrate; depositing, by a second atomic layer deposition method, a second material deposition layer over the first deposition layer, the second material composition being different than the first material composition; wherein each of the first and the second atomic layer deposition methods is performed at a reaction temperature of between 80 ° C and 800 ° C and each of the deposition layers is characterized by an as applied crystal lattice structure; and heating at least one of the first and second deposition layers to an annealing temperature above 900 ° C for less than 20 msec to alter the as applied crystal lattice of the heated deposition layer. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the first material deposition layer and a single crystal lattice spacing of the silicon substrate are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the second material deposition layer and a single crystal lattice spacing of the first material deposition layer are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein the composition of at least one of the first material deposition layer and the second material deposition layer comprises one of a group III -V, group I I-VI, or a group III -N material. Original
The solid state element of claim 17 wherein the second material deposition layer comprises one of silicon carbide, gallium nitride, or diamond. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride. Original
The solid state element of claim 17 wherein the first material deposition layer comprises yttrium oxide and the second material deposition layer comprises zinc oxide. Original
The solid state element of claim 17 wherein the method further comprises depositing a transition material deposition layer on the first material deposition layer before depositing the second material deposition layer, and wherein the transition material deposition layer comprises a plurality of different material layers each having a different material layer composition and each formed by a different atomic layer deposition process. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride and wherein the method further comprises depositing a boron nitride release layer over the first material deposition layer wherein the boron nitride release layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, depositing a second aluminum nitride layer over the boron nitride release layer wherein the second aluminum nitride layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, and wherein the second material deposition layer has a layer thickness of at least 2.5 m and a minimum breakdown voltage of 100 volts. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si heteroepitaxial stack
solid state element with ALD-deposited heteroepitaxial layers on silicon
Materials described outside the worked examples.
silicon substrate
Si
aluminum nitride nucleation layer
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 80–800 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,491Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface; applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method; applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an Al x Gai-x N compound and wherein each of the plurality of different Al xGai-x N compounds is applied by a different atomic layer deposition method; and applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method. Currently amended
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 800 °C. Original
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 400 °C. Original
The method of claim 1 wherein the silicon substrate comprises a single crystal, wherein the silicon substrate coating surface comprises a crystallographic plane, and wherein the step of applying the gallium nitride device layer over the transition layer creates a material interface characterized by both a coefficient of thermal expansion mismatch and a crystal lattice spacing mismatch, wherein one of the coefficient of thermal expansion mismatch or the crystal lattice spacing mismatch is smaller at the material interface than a coefficient of thermal expansion mismatch or a crystal lattice spacing mismatch at a material interface between gallium nitride deposited on the crystallographic plane of silicon. Original
The method of claim 1 further comprising heating one of the aluminum nitride nucleation layer, the transition layer, or the gallium nitride device layer to an annealing temperature above 900 ° C for less than 20 msec. Original
cancelled Canceled
The method of claim [[4]] 1 wherein each of the first, the second and the third atomic layer deposition methods and each of the different atomic layer deposition methods used is performed at the same atomic layer deposition reaction temperature. Currently amended
A solid state element formed by a method comprising: depositing, by a first atomic layer deposition method, a first material deposition layer over a coating surface of a silicon substrate; depositing, by a second atomic layer deposition method, a second material deposition layer over the first deposition layer, the second material composition being different than the first material composition; wherein each of the first and the second atomic layer deposition methods is performed at a reaction temperature of between 80 ° C and 800 ° C and each of the deposition layers is characterized by an as applied crystal lattice structure; and heating at least one of the first and second deposition layers to an annealing temperature above 900 ° C for less than 20 msec to alter the as applied crystal lattice of the heated deposition layer. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the first material deposition layer and a single crystal lattice spacing of the silicon substrate are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the second material deposition layer and a single crystal lattice spacing of the first material deposition layer are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein the composition of at least one of the first material deposition layer and the second material deposition layer comprises one of a group III -V, group I I-VI, or a group III -N material. Original
The solid state element of claim 17 wherein the second material deposition layer comprises one of silicon carbide, gallium nitride, or diamond. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride. Original
The solid state element of claim 17 wherein the first material deposition layer comprises yttrium oxide and the second material deposition layer comprises zinc oxide. Original
The solid state element of claim 17 wherein the method further comprises depositing a transition material deposition layer on the first material deposition layer before depositing the second material deposition layer, and wherein the transition material deposition layer comprises a plurality of different material layers each having a different material layer composition and each formed by a different atomic layer deposition process. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride and wherein the method further comprises depositing a boron nitride release layer over the first material deposition layer wherein the boron nitride release layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, depositing a second aluminum nitride layer over the boron nitride release layer wherein the second aluminum nitride layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, and wherein the second material deposition layer has a layer thickness of at least 2.5 m and a minimum breakdown voltage of 100 volts. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si heteroepitaxial stack
solid state element with ALD-deposited heteroepitaxial layers on silicon
Materials described outside the worked examples.
silicon substrate
Si
aluminum nitride nucleation layer
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 80–800 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,491Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: supporting a silicon substrate inside a deposition chamber, the silicon substrate including a silicon substrate coating surface; applying an aluminum nitride nucleation layer onto the silicon substrate coating surface using a first atomic layer deposition method; applying a transition layer over the aluminum nitride nucleation layer using a second atomic layer deposition method, wherein applying the transition layer comprises applying a plurality of different material layers wherein each of the plurality of different material layers comprises an Al x Gai-x N compound and wherein each of the plurality of different Al xGai-x N compounds is applied by a different atomic layer deposition method; and applying a gallium nitride device layer over the transition layer using a third atomic layer deposition method. Currently amended
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 800 °C. Original
The method of claim 1 wherein an atomic layer deposition reaction temperature for each of the first, second, and third atomic layer deposition methods is between 80 ° C and 400 °C. Original
The method of claim 1 wherein the silicon substrate comprises a single crystal, wherein the silicon substrate coating surface comprises a crystallographic plane, and wherein the step of applying the gallium nitride device layer over the transition layer creates a material interface characterized by both a coefficient of thermal expansion mismatch and a crystal lattice spacing mismatch, wherein one of the coefficient of thermal expansion mismatch or the crystal lattice spacing mismatch is smaller at the material interface than a coefficient of thermal expansion mismatch or a crystal lattice spacing mismatch at a material interface between gallium nitride deposited on the crystallographic plane of silicon. Original
The method of claim 1 further comprising heating one of the aluminum nitride nucleation layer, the transition layer, or the gallium nitride device layer to an annealing temperature above 900 ° C for less than 20 msec. Original
cancelled Canceled
The method of claim [[4]] 1 wherein each of the first, the second and the third atomic layer deposition methods and each of the different atomic layer deposition methods used is performed at the same atomic layer deposition reaction temperature. Currently amended
A solid state element formed by a method comprising: depositing, by a first atomic layer deposition method, a first material deposition layer over a coating surface of a silicon substrate; depositing, by a second atomic layer deposition method, a second material deposition layer over the first deposition layer, the second material composition being different than the first material composition; wherein each of the first and the second atomic layer deposition methods is performed at a reaction temperature of between 80 ° C and 800 ° C and each of the deposition layers is characterized by an as applied crystal lattice structure; and heating at least one of the first and second deposition layers to an annealing temperature above 900 ° C for less than 20 msec to alter the as applied crystal lattice of the heated deposition layer. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the first material deposition layer and a single crystal lattice spacing of the silicon substrate are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein a single crystal lattice spacing of the second material deposition layer and a single crystal lattice spacing of the first material deposition layer are matched at integral multiples of at least one major crystal lattice plane. Original
The solid state element of claim 17 wherein the composition of at least one of the first material deposition layer and the second material deposition layer comprises one of a group III -V, group I I-VI, or a group III -N material. Original
The solid state element of claim 17 wherein the second material deposition layer comprises one of silicon carbide, gallium nitride, or diamond. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride. Original
The solid state element of claim 17 wherein the first material deposition layer comprises yttrium oxide and the second material deposition layer comprises zinc oxide. Original
The solid state element of claim 17 wherein the method further comprises depositing a transition material deposition layer on the first material deposition layer before depositing the second material deposition layer, and wherein the transition material deposition layer comprises a plurality of different material layers each having a different material layer composition and each formed by a different atomic layer deposition process. Original
The solid state element of claim 17 wherein the first material deposition layer comprises aluminum nitride and the second material deposition layer comprises gallium nitride and wherein the method further comprises depositing a boron nitride release layer over the first material deposition layer wherein the boron nitride release layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, depositing a second aluminum nitride layer over the boron nitride release layer wherein the second aluminum nitride layer is formed by an atomic layer deposition process at a reaction temperature of between 80 ° C and 800 °C, and wherein the second material deposition layer has a layer thickness of at least 2.5 m and a minimum breakdown voltage of 100 volts. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si heteroepitaxial stack
solid state element with ALD-deposited heteroepitaxial layers on silicon
Materials described outside the worked examples.
silicon substrate
Si
aluminum nitride nucleation layer
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 80–800 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
AlxGa₁-xN transition layer
AlxGa₁-xN
gallium nitride device layer
GaN
group III-V, II-VI, or III-N material
silicon carbide
SiC
diamond
C
yttrium oxide
Y₂O₃
zinc oxide
ZnO
boron nitride release layer
BN
| — |
Thickness | 515–580 nm | — |
Pressure | 1–500 mTorr | — |
Temperature | ≤ 900 °C | — |
AlxGa₁-xN transition layer
AlxGa₁-xN
gallium nitride device layer
GaN
group III-V, II-VI, or III-N material
silicon carbide
SiC
diamond
C
yttrium oxide
Y₂O₃
zinc oxide
ZnO
boron nitride release layer
BN
| — |
Thickness | 515–580 nm | — |
Pressure | 1–500 mTorr | — |
Temperature | ≤ 900 °C | — |
AlxGa₁-xN transition layer
AlxGa₁-xN
gallium nitride device layer
GaN
group III-V, II-VI, or III-N material
silicon carbide
SiC
diamond
C
yttrium oxide
Y₂O₃
zinc oxide
ZnO
boron nitride release layer
BN
| — |
Thickness | 515–580 nm | — |
Pressure | 1–500 mTorr | — |
Temperature | ≤ 900 °C | — |
AlxGa₁-xN transition layer
AlxGa₁-xN
gallium nitride device layer
GaN
group III-V, II-VI, or III-N material
silicon carbide
SiC
diamond
C
yttrium oxide
Y₂O₃
zinc oxide
ZnO
boron nitride release layer
BN
| — |
Thickness | 515–580 nm | — |
Pressure | 1–500 mTorr | — |
Temperature | ≤ 900 °C | — |