Patent
Atlas literature
Patent
US 9,768,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
FIG. 2 depicts a semiconductor with a p-i-n diode and a multiplication layer, according to an illustrative implementation; [0014]
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 4 depicts a semiconductor with a GaAs-based p-i-n diode and a multiplication layer, according to an illustrative implementation; [0016]
FIG. 5 depicts a graph that shows the characterization of the semiconductor shown in
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 10 depicts a graph that shows the effect of growth temperature and As flux on the carrier concentration of InGaNAsSb, as measured by the Hall effect, …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor, comprising: a substrate with a lattice parameter matching or nearly matching GaAs; a first doped I II -V layer over the substrate; an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGa I N A s l --,Sb, (0 < x < 1; 0 <y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and a second doped I II -V layer over the absorber layer.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3. 2 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.
The semiconductor of claim 1, further comprising a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The semiconductor of claim 1, wherein the substrate comprises GaAs.
The semiconductor of claim 1, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The semiconductor of claim 1, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The semiconductor of claim 1, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type. 3 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein the absorber layer is p-type.
2-3. canceled
canceled
The semiconductor of claim [[2]] 1, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y 0.1; [[0< z< 0.1]] 0< z< 0.1).
A method of forming a semiconductor, comprising: forming a first doped I II -V layer over a substrate with a lattice parameter matching or nearly matching GaAs; forming an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGap X N y As i-y-Z Sb, (0 < x < 1: 0 < y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and forming a second doped I II -V layer over the absorber layer.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers. 4 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of December 2,
The method of claim 16, further comprising forming a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The method of claim 16, wherein the substrate comprises GaAs.
The method of claim 16, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The method of claim 16, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The method of claim 16, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type.
17-18. canceled
canceled
The method of claim [[17]] 16, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y< 0.1; [[0< z< 0.1]] 0< z< 0.1).
Layer stacks claimed or described, ordered top of device to substrate.
p-i-n photodiode semiconductor
avalanche photodiode semiconductor with multiplication layer
Materials described outside the worked examples.
InGaNAsSb dilute nitride
InxGa₁-xNyAs₁-y-zSbz
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7–0.95 eV | InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8–0.95 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,768,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
FIG. 2 depicts a semiconductor with a p-i-n diode and a multiplication layer, according to an illustrative implementation; [0014]
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 4 depicts a semiconductor with a GaAs-based p-i-n diode and a multiplication layer, according to an illustrative implementation; [0016]
FIG. 5 depicts a graph that shows the characterization of the semiconductor shown in
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 10 depicts a graph that shows the effect of growth temperature and As flux on the carrier concentration of InGaNAsSb, as measured by the Hall effect, …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor, comprising: a substrate with a lattice parameter matching or nearly matching GaAs; a first doped I II -V layer over the substrate; an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGa I N A s l --,Sb, (0 < x < 1; 0 <y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and a second doped I II -V layer over the absorber layer.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3. 2 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.
The semiconductor of claim 1, further comprising a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The semiconductor of claim 1, wherein the substrate comprises GaAs.
The semiconductor of claim 1, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The semiconductor of claim 1, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The semiconductor of claim 1, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type. 3 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein the absorber layer is p-type.
2-3. canceled
canceled
The semiconductor of claim [[2]] 1, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y 0.1; [[0< z< 0.1]] 0< z< 0.1).
A method of forming a semiconductor, comprising: forming a first doped I II -V layer over a substrate with a lattice parameter matching or nearly matching GaAs; forming an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGap X N y As i-y-Z Sb, (0 < x < 1: 0 < y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and forming a second doped I II -V layer over the absorber layer.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers. 4 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of December 2,
The method of claim 16, further comprising forming a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The method of claim 16, wherein the substrate comprises GaAs.
The method of claim 16, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The method of claim 16, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The method of claim 16, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type.
17-18. canceled
canceled
The method of claim [[17]] 16, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y< 0.1; [[0< z< 0.1]] 0< z< 0.1).
Layer stacks claimed or described, ordered top of device to substrate.
p-i-n photodiode semiconductor
avalanche photodiode semiconductor with multiplication layer
Materials described outside the worked examples.
InGaNAsSb dilute nitride
InxGa₁-xNyAs₁-y-zSbz
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7–0.95 eV | InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8–0.95 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,768,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
FIG. 2 depicts a semiconductor with a p-i-n diode and a multiplication layer, according to an illustrative implementation; [0014]
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 4 depicts a semiconductor with a GaAs-based p-i-n diode and a multiplication layer, according to an illustrative implementation; [0016]
FIG. 5 depicts a graph that shows the characterization of the semiconductor shown in
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 10 depicts a graph that shows the effect of growth temperature and As flux on the carrier concentration of InGaNAsSb, as measured by the Hall effect, …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor, comprising: a substrate with a lattice parameter matching or nearly matching GaAs; a first doped I II -V layer over the substrate; an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGa I N A s l --,Sb, (0 < x < 1; 0 <y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and a second doped I II -V layer over the absorber layer.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3. 2 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.
The semiconductor of claim 1, further comprising a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The semiconductor of claim 1, wherein the substrate comprises GaAs.
The semiconductor of claim 1, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The semiconductor of claim 1, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The semiconductor of claim 1, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type. 3 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein the absorber layer is p-type.
2-3. canceled
canceled
The semiconductor of claim [[2]] 1, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y 0.1; [[0< z< 0.1]] 0< z< 0.1).
A method of forming a semiconductor, comprising: forming a first doped I II -V layer over a substrate with a lattice parameter matching or nearly matching GaAs; forming an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGap X N y As i-y-Z Sb, (0 < x < 1: 0 < y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and forming a second doped I II -V layer over the absorber layer.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers. 4 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of December 2,
The method of claim 16, further comprising forming a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The method of claim 16, wherein the substrate comprises GaAs.
The method of claim 16, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The method of claim 16, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The method of claim 16, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type.
17-18. canceled
canceled
The method of claim [[17]] 16, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y< 0.1; [[0< z< 0.1]] 0< z< 0.1).
Layer stacks claimed or described, ordered top of device to substrate.
p-i-n photodiode semiconductor
avalanche photodiode semiconductor with multiplication layer
Materials described outside the worked examples.
InGaNAsSb dilute nitride
InxGa₁-xNyAs₁-y-zSbz
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7–0.95 eV | InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8–0.95 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,768,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
FIG. 2 depicts a semiconductor with a p-i-n diode and a multiplication layer, according to an illustrative implementation; [0014]
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 4 depicts a semiconductor with a GaAs-based p-i-n diode and a multiplication layer, according to an illustrative implementation; [0016]
FIG. 5 depicts a graph that shows the characterization of the semiconductor shown in
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 10 depicts a graph that shows the effect of growth temperature and As flux on the carrier concentration of InGaNAsSb, as measured by the Hall effect, …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor, comprising: a substrate with a lattice parameter matching or nearly matching GaAs; a first doped I II -V layer over the substrate; an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGa I N A s l --,Sb, (0 < x < 1; 0 <y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and a second doped I II -V layer over the absorber layer.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The semiconductor of claim 1, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3. 2 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The semiconductor of claim 1, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers.
The semiconductor of claim 1, further comprising a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The semiconductor of claim 1, wherein the substrate comprises GaAs.
The semiconductor of claim 1, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The semiconductor of claim 1, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The semiconductor of claim 1, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type. 3 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of
The semiconductor of claim 1, wherein the absorber layer is p-type.
2-3. canceled
canceled
The semiconductor of claim [[2]] 1, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y 0.1; [[0< z< 0.1]] 0< z< 0.1).
A method of forming a semiconductor, comprising: forming a first doped I II -V layer over a substrate with a lattice parameter matching or nearly matching GaAs; forming an absorber layer over the first doped I II -V layer, the absorber layer having: a dilute nitride comprising InGap X N y As i-y-Z Sb, (0 < x < 1: 0 < y < 0.1; 0 < z < 0.1667) an In/Sb ratio of at least approximately 6, a bandgap between approximately 0.7 eV and 0.95 eV, and a carrier concentration less than approximately 1 x 10 16 cm- 3 at room temperature; and forming a second doped I II -V layer over the absorber layer.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 5 x 10 15 cm- 3.
The method of claim 16, wherein the carrier concentration of the absorber layer is less than approximately 1 x 10 15 cm- 3.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 2 micrometers and approximately 10 micrometers.
The method of claim 16, wherein a thickness of the absorber layer is between approximately 3 micrometers and approximately 5 micrometers. 4 604463111 Application No. 15/188,396 Docket No.: 111848-0002-101 Amendment dated Reply to Office Action of December 2,
The method of claim 16, further comprising forming a multiplication layer between the absorber layer and one of the first and second doped I II -V layers.
The method of claim 16, wherein the substrate comprises GaAs.
The method of claim 16, wherein the substrate comprises: a silicon substrate; and a lattice engineered layer over the silicon substrate, the surface of the lattice engineered layer opposite the silicon substrate having a lattice parameter that is matched or nearly matched to GaAs.
The method of claim 16, wherein the first doped I II -V layer is n-type and the second doped I II -V layer is p-type.
The method of claim 16, wherein the first doped I II -V layer is p-type and the second doped I II -V layer is n-type.
17-18. canceled
canceled
The method of claim [[17]] 16, wherein the dilute nitride comprises In x Gai- x N y Asi- y-z Sb (0 x< 0.55; [[0 < y < 0.1]] 0< y< 0.1; [[0< z< 0.1]] 0< z< 0.1).
Layer stacks claimed or described, ordered top of device to substrate.
p-i-n photodiode semiconductor
avalanche photodiode semiconductor with multiplication layer
Materials described outside the worked examples.
InGaNAsSb dilute nitride
InxGa₁-xNyAs₁-y-zSbz
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a semiconductor 100 comprising a p-i-n diode. The semiconductor 100 includes a substrate 114, an n + III-V layer 112 epitaxially formed over the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0.7–0.95 eV | InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8–0.95 eV |
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SixGe₁-x graded layer
SixGe₁-x
rare earth containing layer
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8 eV | InxGa₁-xNyAs₁-y-zSbz |
Thickness | 2–10 µm | — |
Thickness | 3–5 µm | — |
III-V doped layer
silicon substrate with lattice engineered layer
SixGe₁-x graded layer
SixGe₁-x
rare earth containing layer
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8 eV | InxGa₁-xNyAs₁-y-zSbz |
Thickness | 2–10 µm | — |
Thickness | 3–5 µm | — |
III-V doped layer
silicon substrate with lattice engineered layer
SixGe₁-x graded layer
SixGe₁-x
rare earth containing layer
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8 eV | InxGa₁-xNyAs₁-y-zSbz |
Thickness | 2–10 µm | — |
Thickness | 3–5 µm | — |
III-V doped layer
silicon substrate with lattice engineered layer
SixGe₁-x graded layer
SixGe₁-x
rare earth containing layer
FIG. 3 depicts a semiconductor with a GaAs-based p-i-n diode, according to an illustrative implementation; [0015]
FIG. 6 depicts a graph that shows XRD scans of intrinsic InGaNAsSb layers of different thicknesses epitaxially formed on GaAs, according to an illustrative …
FIG. 7 depicts a graph that shows XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates, according to an illustrative …
FIG. 8 depicts a graph showing the effect of the In/Sb ratio on carrier properties of InGaNAsSb, as measured by the Hall effect, according to an illustrative …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 9 depicts a graph showing the effect of the In/Sb ratio on optical properties of InGaNAsSb, as measured by photoluminescence (PL), according to an …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 11 depicts a graph that shows the effect of growth temperature and arsenic flux on the bandgap of InGaNAsSb, as measured by photoluminescence, according to …
FIG. 12 depicts a graph showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb, as measured by the Hall effect, according …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 13 includes a graph showing the effect of RTA on the bandgap of InGaNAsSb as measured by photoluminescence, according to an illustrative implementation; …
FIG. 14 depicts a graph that shows a photoluminescence spectrum of a 0.5 p m layer of InGaNAsSb grown on a GaAs substrate, according to an illustrative …
FIG. 15 includes a colormap that shows cross-wafer variation in bandgap of a 0.5 pm layer of InGaNAsSb grown on a 150 mm GaAs substrate, according to an …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
FIG. 16. The dilute nitride layer 106 is an intrinsic layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption …
InxGa₁-xNyAs₁-y-zSbz |
Optical Band Gap | 0.8 eV | InxGa₁-xNyAs₁-y-zSbz |
Thickness | 2–10 µm | — |
Thickness | 3–5 µm | — |
