Patent
Atlas literature
Patent
US 9,748,094Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor compound structure according to an exemplary embodiment; [18]
FIG. 2 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [19]
FIG. 3 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [20]
FIG. 4 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [21]
FIG. 5 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [22]
FIG. 6 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [23]
FIG. 7 is a cross-sectional view of a light emitting device according to an exemplary embodiment; [24]
FIG. 8 is a cross-sectional view of a light emitting device according to another exemplary embodiment; [25]
FIG. 9 is a cross-sectional view of a light emitting device according to another exemplary embodiment; and [26]
FIG. 10 is a cross-sectional view of a light emitting device according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q₁₂₁₆₉₅ App l n. No.: 13/095,122 AMENDMENTS TO THE CLAIMS This listing of claims will replace all prior versions and listings of claims in the application: LISTING OF CLAIMS:
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: A semiconductor device comprising: a substrate having a first surface; a lower electrode disposed above the first surface of the substrate; a buffer layer disposed on the lower electrode and above the first surface of the substrate, and comprising carbons having hexagonal crystal structures; a light emission layer formed on the buffer layer, and formed of a semiconductor compound; an insulating layer formed to bury a lower portion of the light emission layer on the buffer layer; and an upper electrode formed to cover the light emission layer and the insulating layer.
: The semiconductor device of claim 19, further comprising a wetting layer formed on the buffer layer for depositing the light emission layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a first semiconductor layer formed on the buffer layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a group I II -V compound semiconductor material.
: The semiconductor device of claim 19, wherein the buffer layer comprises graphene or graphite.
: The semiconductor device of claim 19, wherein the buffer layer comprises carbon nanotubes (CNTs).
: The semiconductor device of claim 19, further comprising a resistive layer between the lower electrode and the buffer layer.
: The semiconductor device of claim 19, further comprising a catalyst layer on the lower electrode for forming the buffer layer.
: The semiconductor device of claim 19, wherein the lower electrode is formed on an upper surface of the substrate.
: The semiconductor device of claim 19, wherein the lower electrode is disposed to be separated from the substrate, and the insulating layer fills a space between the substrate and the lower electrode.
Claims 31-35. 4 canceled
canceled
canceled
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Layer stacks claimed or described, ordered top of device to substrate.
semiconductor light emitting device
Materials described outside the worked examples.
graphene or graphite
carbon nanotubes (CNTs)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–600 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,748,094Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor compound structure according to an exemplary embodiment; [18]
FIG. 2 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [19]
FIG. 3 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [20]
FIG. 4 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [21]
FIG. 5 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [22]
FIG. 6 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [23]
FIG. 7 is a cross-sectional view of a light emitting device according to an exemplary embodiment; [24]
FIG. 8 is a cross-sectional view of a light emitting device according to another exemplary embodiment; [25]
FIG. 9 is a cross-sectional view of a light emitting device according to another exemplary embodiment; and [26]
FIG. 10 is a cross-sectional view of a light emitting device according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q₁₂₁₆₉₅ App l n. No.: 13/095,122 AMENDMENTS TO THE CLAIMS This listing of claims will replace all prior versions and listings of claims in the application: LISTING OF CLAIMS:
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: A semiconductor device comprising: a substrate having a first surface; a lower electrode disposed above the first surface of the substrate; a buffer layer disposed on the lower electrode and above the first surface of the substrate, and comprising carbons having hexagonal crystal structures; a light emission layer formed on the buffer layer, and formed of a semiconductor compound; an insulating layer formed to bury a lower portion of the light emission layer on the buffer layer; and an upper electrode formed to cover the light emission layer and the insulating layer.
: The semiconductor device of claim 19, further comprising a wetting layer formed on the buffer layer for depositing the light emission layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a first semiconductor layer formed on the buffer layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a group I II -V compound semiconductor material.
: The semiconductor device of claim 19, wherein the buffer layer comprises graphene or graphite.
: The semiconductor device of claim 19, wherein the buffer layer comprises carbon nanotubes (CNTs).
: The semiconductor device of claim 19, further comprising a resistive layer between the lower electrode and the buffer layer.
: The semiconductor device of claim 19, further comprising a catalyst layer on the lower electrode for forming the buffer layer.
: The semiconductor device of claim 19, wherein the lower electrode is formed on an upper surface of the substrate.
: The semiconductor device of claim 19, wherein the lower electrode is disposed to be separated from the substrate, and the insulating layer fills a space between the substrate and the lower electrode.
Claims 31-35. 4 canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor light emitting device
Materials described outside the worked examples.
graphene or graphite
carbon nanotubes (CNTs)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–600 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,748,094Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor compound structure according to an exemplary embodiment; [18]
FIG. 2 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [19]
FIG. 3 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [20]
FIG. 4 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [21]
FIG. 5 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [22]
FIG. 6 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [23]
FIG. 7 is a cross-sectional view of a light emitting device according to an exemplary embodiment; [24]
FIG. 8 is a cross-sectional view of a light emitting device according to another exemplary embodiment; [25]
FIG. 9 is a cross-sectional view of a light emitting device according to another exemplary embodiment; and [26]
FIG. 10 is a cross-sectional view of a light emitting device according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q₁₂₁₆₉₅ App l n. No.: 13/095,122 AMENDMENTS TO THE CLAIMS This listing of claims will replace all prior versions and listings of claims in the application: LISTING OF CLAIMS:
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: A semiconductor device comprising: a substrate having a first surface; a lower electrode disposed above the first surface of the substrate; a buffer layer disposed on the lower electrode and above the first surface of the substrate, and comprising carbons having hexagonal crystal structures; a light emission layer formed on the buffer layer, and formed of a semiconductor compound; an insulating layer formed to bury a lower portion of the light emission layer on the buffer layer; and an upper electrode formed to cover the light emission layer and the insulating layer.
: The semiconductor device of claim 19, further comprising a wetting layer formed on the buffer layer for depositing the light emission layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a first semiconductor layer formed on the buffer layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a group I II -V compound semiconductor material.
: The semiconductor device of claim 19, wherein the buffer layer comprises graphene or graphite.
: The semiconductor device of claim 19, wherein the buffer layer comprises carbon nanotubes (CNTs).
: The semiconductor device of claim 19, further comprising a resistive layer between the lower electrode and the buffer layer.
: The semiconductor device of claim 19, further comprising a catalyst layer on the lower electrode for forming the buffer layer.
: The semiconductor device of claim 19, wherein the lower electrode is formed on an upper surface of the substrate.
: The semiconductor device of claim 19, wherein the lower electrode is disposed to be separated from the substrate, and the insulating layer fills a space between the substrate and the lower electrode.
Claims 31-35. 4 canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor light emitting device
Materials described outside the worked examples.
graphene or graphite
carbon nanotubes (CNTs)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–600 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,748,094Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor compound structure according to an exemplary embodiment; [18]
FIG. 2 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [19]
FIG. 3 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [20]
FIG. 4 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [21]
FIG. 5 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [22]
FIG. 6 is a cross-sectional view of a semiconductor compound structure according to another exemplary embodiment; [23]
FIG. 7 is a cross-sectional view of a light emitting device according to an exemplary embodiment; [24]
FIG. 8 is a cross-sectional view of a light emitting device according to another exemplary embodiment; [25]
FIG. 9 is a cross-sectional view of a light emitting device according to another exemplary embodiment; and [26]
FIG. 10 is a cross-sectional view of a light emitting device according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q₁₂₁₆₉₅ App l n. No.: 13/095,122 AMENDMENTS TO THE CLAIMS This listing of claims will replace all prior versions and listings of claims in the application: LISTING OF CLAIMS:
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
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canceled
canceled
canceled
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canceled
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: A semiconductor device comprising: a substrate having a first surface; a lower electrode disposed above the first surface of the substrate; a buffer layer disposed on the lower electrode and above the first surface of the substrate, and comprising carbons having hexagonal crystal structures; a light emission layer formed on the buffer layer, and formed of a semiconductor compound; an insulating layer formed to bury a lower portion of the light emission layer on the buffer layer; and an upper electrode formed to cover the light emission layer and the insulating layer.
: The semiconductor device of claim 19, further comprising a wetting layer formed on the buffer layer for depositing the light emission layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a first semiconductor layer formed on the buffer layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer.
: The semiconductor device of claim 19, wherein the light emission layer comprises a group I II -V compound semiconductor material.
: The semiconductor device of claim 19, wherein the buffer layer comprises graphene or graphite.
: The semiconductor device of claim 19, wherein the buffer layer comprises carbon nanotubes (CNTs).
: The semiconductor device of claim 19, further comprising a resistive layer between the lower electrode and the buffer layer.
: The semiconductor device of claim 19, further comprising a catalyst layer on the lower electrode for forming the buffer layer.
: The semiconductor device of claim 19, wherein the lower electrode is formed on an upper surface of the substrate.
: The semiconductor device of claim 19, wherein the lower electrode is disposed to be separated from the substrate, and the insulating layer fills a space between the substrate and the lower electrode.
Claims 31-35. 4 canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor light emitting device
Materials described outside the worked examples.
graphene or graphite
carbon nanotubes (CNTs)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 500–600 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
semiconductor compound structure with graphene buffer layer
semiconductor compound structure with CNT buffer layer
wetting layer
group III-V compound semiconductor material
catalyst layer
gallium nitride (GaN)
GaN
AlN
ZnO
Al₂O₃
copper foil
Cu
Cu, Ni, or Invar (alloy of Fe and Ni)
| 1000–1100 °C |
| — |
Casimir-like effect driven self-assembly of graphene on molten metals
semiconductor compound structure with graphene buffer layer
semiconductor compound structure with CNT buffer layer
wetting layer
group III-V compound semiconductor material
catalyst layer
gallium nitride (GaN)
GaN
AlN
ZnO
Al₂O₃
copper foil
Cu
Cu, Ni, or Invar (alloy of Fe and Ni)
| 1000–1100 °C |
| — |
Casimir-like effect driven self-assembly of graphene on molten metals
semiconductor compound structure with graphene buffer layer
semiconductor compound structure with CNT buffer layer
wetting layer
group III-V compound semiconductor material
catalyst layer
gallium nitride (GaN)
GaN
AlN
ZnO
Al₂O₃
copper foil
Cu
Cu, Ni, or Invar (alloy of Fe and Ni)
| 1000–1100 °C |
| — |
Casimir-like effect driven self-assembly of graphene on molten metals
semiconductor compound structure with graphene buffer layer
semiconductor compound structure with CNT buffer layer
wetting layer
group III-V compound semiconductor material
catalyst layer
gallium nitride (GaN)
GaN
AlN
ZnO
Al₂O₃
copper foil
Cu
Cu, Ni, or Invar (alloy of Fe and Ni)
| 1000–1100 °C |
| — |
