Patent
US 9,184,258SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Akira Yoshioka
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,184,258Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; [0006]
FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a modification of the first 30 embodiment; [0007]
FIG. 3 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment; [0008]
FIG. 4 is a schematic cross-sectional view illustrating 1 ADG067087(FTS0939) the method of manufacturing the semiconductor device according to the first …
FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according 5 to the first embodiment; [0010]
FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment; [0011]
FIG. 7 is a schematic cross-sectional view of a 10 semiconductor device according to a second embodiment; [0012]
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; [0013]
FIG. 9 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according 15 to the third embodiment; [0014]
FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment; [0015]
FIG. 11 is a schematic cross-sectional view of a 20 semiconductor device according to a fifth embodiment; [0016]
FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the fifth embodiment; [0017]
FIG. 13 is a schematic cross-sectional view 25 illustrating a method of manufacturing a semiconductor device according to a sixth embodiment; and [0018]
FIG. 14 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the sixth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor device comprising: an n-type first G aN-based semiconductor layer; a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of l aye r above the low impurity concentration region; a gate electrode having one end thereof located at the third G aN-based semiconductor layer or in a higher position than the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer, the gate electrode being located adjacent to the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer intervening a gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and 3 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858921.1.301.247.2246.379.svg 0.44 6.483 Drawing Black and white a third electrode provided at the o pposite side -f below the first GaN-based semiconductor layer.
The semiconductor device according to claim 1, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer is an epitaxially grown layer.
canceled
canceled
(Cu rr ently Amended) A semiconductor device comprising: an n-type first GaN-based semiconductor layer; 4 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858922.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of layer above the low impurity concentration region; a trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; a gate insulating film provided on an inner wall of the trench, the inner wall being provided with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; a gate electrode provided above the gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and a third electrode provided at the oppo site side o below the first G aN-based semiconductor layer. 5 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858923.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white
The semiconductor device according to claim 9, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
canceled
canceled
A method of manufacturing a semiconductor device comprising: forming a p-type second GaN-based semiconductor layer on an n-type first GaN- based semiconductor layer by an epitaxial growth, the p-type second GaN-based semiconductor layer being made to include a low impurity concentration region on a side of the first GaN-based semiconductor layer and a high impurity concentration region on the opposite side from the first GaN-based semiconductor layer by varying a p-type impurity concentration in a source gas from a low concentration to a high concentration; 6 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858924.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white forming an n-type third G aN-based semiconductor layer formed on the opposite side of the second G aN-based semiconductor layer from the first G aN-based semiconductor layer; forming a first trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; forming a gate insulating film on an inner wall of the first trench, the inner wall being formed with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; forming a gate electrode on the gate insulating film; forming a first electrode on the third G aN-based semiconductor layer; forming a second electrode on the high impurity concentration region; and forming a third electrode on the opposite side of the first G aN-based semiconductor layer from the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, wherein the third G aN-based semiconductor layer is formed by implanting n-type impurity ions into the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, further comprising forming a second trench in the second G aN-based semiconductor layer prior to the formation of the first trench, the second trench having such a depth that the second trench does not reach the first G aN-based semiconductor layer, 7 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858925.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white wherein the third GaN-based semiconductor layer is formed by forming a GaN- based semiconductor layer in the second trench by an epitaxial growth technique. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based vertical MOSFET (trench gate, n-channel) — claim 1 variant
GaN-based vertical trench-gate MOSFET (n-channel) — claim 9 variant with explicit trench
Materials described outside the worked examples.
n-type GaN-based semiconductor layer (first, drift/drain)
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thickness of n-type GaN substrate | 50–200 µm | GaN |
thickness of n-type GaN drift layer (first GaN-based semiconductor layer) | 4–25 µm |
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US 9,184,258Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; [0006]
FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a modification of the first 30 embodiment; [0007]
FIG. 3 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment; [0008]
FIG. 4 is a schematic cross-sectional view illustrating 1 ADG067087(FTS0939) the method of manufacturing the semiconductor device according to the first …
FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according 5 to the first embodiment; [0010]
FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment; [0011]
FIG. 7 is a schematic cross-sectional view of a 10 semiconductor device according to a second embodiment; [0012]
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; [0013]
FIG. 9 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according 15 to the third embodiment; [0014]
FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment; [0015]
FIG. 11 is a schematic cross-sectional view of a 20 semiconductor device according to a fifth embodiment; [0016]
FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the fifth embodiment; [0017]
FIG. 13 is a schematic cross-sectional view 25 illustrating a method of manufacturing a semiconductor device according to a sixth embodiment; and [0018]
FIG. 14 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the sixth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor device comprising: an n-type first G aN-based semiconductor layer; a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of l aye r above the low impurity concentration region; a gate electrode having one end thereof located at the third G aN-based semiconductor layer or in a higher position than the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer, the gate electrode being located adjacent to the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer intervening a gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and 3 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858921.1.301.247.2246.379.svg 0.44 6.483 Drawing Black and white a third electrode provided at the o pposite side -f below the first GaN-based semiconductor layer.
The semiconductor device according to claim 1, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer is an epitaxially grown layer.
canceled
canceled
(Cu rr ently Amended) A semiconductor device comprising: an n-type first GaN-based semiconductor layer; 4 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858922.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of layer above the low impurity concentration region; a trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; a gate insulating film provided on an inner wall of the trench, the inner wall being provided with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; a gate electrode provided above the gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and a third electrode provided at the oppo site side o below the first G aN-based semiconductor layer. 5 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858923.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white
The semiconductor device according to claim 9, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
canceled
canceled
A method of manufacturing a semiconductor device comprising: forming a p-type second GaN-based semiconductor layer on an n-type first GaN- based semiconductor layer by an epitaxial growth, the p-type second GaN-based semiconductor layer being made to include a low impurity concentration region on a side of the first GaN-based semiconductor layer and a high impurity concentration region on the opposite side from the first GaN-based semiconductor layer by varying a p-type impurity concentration in a source gas from a low concentration to a high concentration; 6 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858924.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white forming an n-type third G aN-based semiconductor layer formed on the opposite side of the second G aN-based semiconductor layer from the first G aN-based semiconductor layer; forming a first trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; forming a gate insulating film on an inner wall of the first trench, the inner wall being formed with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; forming a gate electrode on the gate insulating film; forming a first electrode on the third G aN-based semiconductor layer; forming a second electrode on the high impurity concentration region; and forming a third electrode on the opposite side of the first G aN-based semiconductor layer from the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, wherein the third G aN-based semiconductor layer is formed by implanting n-type impurity ions into the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, further comprising forming a second trench in the second G aN-based semiconductor layer prior to the formation of the first trench, the second trench having such a depth that the second trench does not reach the first G aN-based semiconductor layer, 7 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858925.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white wherein the third GaN-based semiconductor layer is formed by forming a GaN- based semiconductor layer in the second trench by an epitaxial growth technique. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based vertical MOSFET (trench gate, n-channel) — claim 1 variant
GaN-based vertical trench-gate MOSFET (n-channel) — claim 9 variant with explicit trench
Materials described outside the worked examples.
n-type GaN-based semiconductor layer (first, drift/drain)
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thickness of n-type GaN substrate | 50–200 µm | GaN |
thickness of n-type GaN drift layer (first GaN-based semiconductor layer) | 4–25 µm |
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Atlas literature
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US 9,184,258Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; [0006]
FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a modification of the first 30 embodiment; [0007]
FIG. 3 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment; [0008]
FIG. 4 is a schematic cross-sectional view illustrating 1 ADG067087(FTS0939) the method of manufacturing the semiconductor device according to the first …
FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according 5 to the first embodiment; [0010]
FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment; [0011]
FIG. 7 is a schematic cross-sectional view of a 10 semiconductor device according to a second embodiment; [0012]
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; [0013]
FIG. 9 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according 15 to the third embodiment; [0014]
FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment; [0015]
FIG. 11 is a schematic cross-sectional view of a 20 semiconductor device according to a fifth embodiment; [0016]
FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the fifth embodiment; [0017]
FIG. 13 is a schematic cross-sectional view 25 illustrating a method of manufacturing a semiconductor device according to a sixth embodiment; and [0018]
FIG. 14 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the sixth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor device comprising: an n-type first G aN-based semiconductor layer; a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of l aye r above the low impurity concentration region; a gate electrode having one end thereof located at the third G aN-based semiconductor layer or in a higher position than the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer, the gate electrode being located adjacent to the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer intervening a gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and 3 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858921.1.301.247.2246.379.svg 0.44 6.483 Drawing Black and white a third electrode provided at the o pposite side -f below the first GaN-based semiconductor layer.
The semiconductor device according to claim 1, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer is an epitaxially grown layer.
canceled
canceled
(Cu rr ently Amended) A semiconductor device comprising: an n-type first GaN-based semiconductor layer; 4 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858922.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of layer above the low impurity concentration region; a trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; a gate insulating film provided on an inner wall of the trench, the inner wall being provided with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; a gate electrode provided above the gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and a third electrode provided at the oppo site side o below the first G aN-based semiconductor layer. 5 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858923.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white
The semiconductor device according to claim 9, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
canceled
canceled
A method of manufacturing a semiconductor device comprising: forming a p-type second GaN-based semiconductor layer on an n-type first GaN- based semiconductor layer by an epitaxial growth, the p-type second GaN-based semiconductor layer being made to include a low impurity concentration region on a side of the first GaN-based semiconductor layer and a high impurity concentration region on the opposite side from the first GaN-based semiconductor layer by varying a p-type impurity concentration in a source gas from a low concentration to a high concentration; 6 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858924.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white forming an n-type third G aN-based semiconductor layer formed on the opposite side of the second G aN-based semiconductor layer from the first G aN-based semiconductor layer; forming a first trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; forming a gate insulating film on an inner wall of the first trench, the inner wall being formed with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; forming a gate electrode on the gate insulating film; forming a first electrode on the third G aN-based semiconductor layer; forming a second electrode on the high impurity concentration region; and forming a third electrode on the opposite side of the first G aN-based semiconductor layer from the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, wherein the third G aN-based semiconductor layer is formed by implanting n-type impurity ions into the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, further comprising forming a second trench in the second G aN-based semiconductor layer prior to the formation of the first trench, the second trench having such a depth that the second trench does not reach the first G aN-based semiconductor layer, 7 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858925.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white wherein the third GaN-based semiconductor layer is formed by forming a GaN- based semiconductor layer in the second trench by an epitaxial growth technique. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based vertical MOSFET (trench gate, n-channel) — claim 1 variant
GaN-based vertical trench-gate MOSFET (n-channel) — claim 9 variant with explicit trench
Materials described outside the worked examples.
n-type GaN-based semiconductor layer (first, drift/drain)
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thickness of n-type GaN substrate | 50–200 µm | GaN |
thickness of n-type GaN drift layer (first GaN-based semiconductor layer) | 4–25 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 9,184,258Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; [0006]
FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a modification of the first 30 embodiment; [0007]
FIG. 3 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment; [0008]
FIG. 4 is a schematic cross-sectional view illustrating 1 ADG067087(FTS0939) the method of manufacturing the semiconductor device according to the first …
FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according 5 to the first embodiment; [0010]
FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment; [0011]
FIG. 7 is a schematic cross-sectional view of a 10 semiconductor device according to a second embodiment; [0012]
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment; [0013]
FIG. 9 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according 15 to the third embodiment; [0014]
FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment; [0015]
FIG. 11 is a schematic cross-sectional view of a 20 semiconductor device according to a fifth embodiment; [0016]
FIG. 12 is a schematic cross-sectional view illustrating a method of manufacturing the semiconductor device according to the fifth embodiment; [0017]
FIG. 13 is a schematic cross-sectional view 25 illustrating a method of manufacturing a semiconductor device according to a sixth embodiment; and [0018]
FIG. 14 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the sixth embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor device comprising: an n-type first G aN-based semiconductor layer; a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of l aye r above the low impurity concentration region; a gate electrode having one end thereof located at the third G aN-based semiconductor layer or in a higher position than the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer, the gate electrode being located adjacent to the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer intervening a gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and 3 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858921.1.301.247.2246.379.svg 0.44 6.483 Drawing Black and white a third electrode provided at the o pposite side -f below the first GaN-based semiconductor layer.
The semiconductor device according to claim 1, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
The semiconductor device according to claim 1, wherein the third GaN-based semiconductor layer is an epitaxially grown layer.
canceled
canceled
(Cu rr ently Amended) A semiconductor device comprising: an n-type first GaN-based semiconductor layer; 4 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858922.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white a p-type second G aN-based semiconductor layer provided above the first G aN- based semiconductor layer, the p-type second G aN-based semiconductor layer including a low impurity concentration region on and a high impurity concentration region on the opposite side, the low impurity concentration region provided between the hi g h impurity concentration region and the first G aN-based semiconductor layer; an n-type third G aN-based semiconductor layer provided at the oppo site side of layer above the low impurity concentration region; a trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; a gate insulating film provided on an inner wall of the trench, the inner wall being provided with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; a gate electrode provided above the gate insulating film; a first electrode provided above the third G aN-based semiconductor layer; a second electrode provided above the high impurity concentration region, the second electrode being a different material from the first electrode; and a third electrode provided at the oppo site side o below the first G aN-based semiconductor layer. 5 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858923.1.301.247.2246.379.svg 0.44 6.483 Graph Black and white
The semiconductor device according to claim 9, wherein the second GaN- based semiconductor layer is an epitaxially grown layer.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer contains a p-type impurity.
The semiconductor device according to claim 9, wherein the third GaN-based semiconductor layer includes an AlGaN layer.
canceled
canceled
A method of manufacturing a semiconductor device comprising: forming a p-type second GaN-based semiconductor layer on an n-type first GaN- based semiconductor layer by an epitaxial growth, the p-type second GaN-based semiconductor layer being made to include a low impurity concentration region on a side of the first GaN-based semiconductor layer and a high impurity concentration region on the opposite side from the first GaN-based semiconductor layer by varying a p-type impurity concentration in a source gas from a low concentration to a high concentration; 6 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858924.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white forming an n-type third G aN-based semiconductor layer formed on the opposite side of the second G aN-based semiconductor layer from the first G aN-based semiconductor layer; forming a first trench having one end thereof located in the third G aN-based semiconductor layer and the other end thereof located in the first G aN-based semiconductor layer; forming a gate insulating film on an inner wall of the first trench, the inner wall being formed with the third G aN-based semiconductor layer, the low impurity concentration region, and the first G aN-based semiconductor layer; forming a gate electrode on the gate insulating film; forming a first electrode on the third G aN-based semiconductor layer; forming a second electrode on the high impurity concentration region; and forming a third electrode on the opposite side of the first G aN-based semiconductor layer from the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, wherein the third G aN-based semiconductor layer is formed by implanting n-type impurity ions into the second G aN-based semiconductor layer. withdrawn
The method according to claim 16, further comprising forming a second trench in the second G aN-based semiconductor layer prior to the formation of the first trench, the second trench having such a depth that the second trench does not reach the first G aN-based semiconductor layer, 7 SVG 14215346.05-18-2015.I₉U₇V₉TJPXXIFW3.CLM16858925.1.301.247.2246.379.svg 0.44 6.483 Chemistry Black and white wherein the third GaN-based semiconductor layer is formed by forming a GaN- based semiconductor layer in the second trench by an epitaxial growth technique. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based vertical MOSFET (trench gate, n-channel) — claim 1 variant
GaN-based vertical trench-gate MOSFET (n-channel) — claim 9 variant with explicit trench
Materials described outside the worked examples.
n-type GaN-based semiconductor layer (first, drift/drain)
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thickness of n-type GaN substrate | 50–200 µm | GaN |
thickness of n-type GaN drift layer (first GaN-based semiconductor layer) | 4–25 µm |
Related documents with shared materials, methods, properties, or citations.
GaN MOSFET 100 (first embodiment, described in detail)
gate insulating film
AlGaN layer
AlxGa₁-xN
gate insulating film (silicon oxide)
SiO₂
gate electrode (p-type or n-type polysilicon)
thickness of low impurity concentration region (channel region) of p-type GaN layer | 0.5–2 µm | GaN |
thickness of high impurity concentration region (channel contact region) of p-type GaN layer | 50–300 nm | GaN |
trench depth | 1–2 µm | — |
gate insulating film (SiO2) thickness | 50–200 nm | SiO₂ |
Thickness | ≥ 300 nm | — |
Thickness | ≥ 200 nm | — |
GaN MOSFET 100 (first embodiment, described in detail)
gate insulating film
AlGaN layer
AlxGa₁-xN
gate insulating film (silicon oxide)
SiO₂
gate electrode (p-type or n-type polysilicon)
thickness of low impurity concentration region (channel region) of p-type GaN layer | 0.5–2 µm | GaN |
thickness of high impurity concentration region (channel contact region) of p-type GaN layer | 50–300 nm | GaN |
trench depth | 1–2 µm | — |
gate insulating film (SiO2) thickness | 50–200 nm | SiO₂ |
Thickness | ≥ 300 nm | — |
Thickness | ≥ 200 nm | — |
GaN MOSFET 100 (first embodiment, described in detail)
gate insulating film
AlGaN layer
AlxGa₁-xN
gate insulating film (silicon oxide)
SiO₂
gate electrode (p-type or n-type polysilicon)
thickness of low impurity concentration region (channel region) of p-type GaN layer | 0.5–2 µm | GaN |
thickness of high impurity concentration region (channel contact region) of p-type GaN layer | 50–300 nm | GaN |
trench depth | 1–2 µm | — |
gate insulating film (SiO2) thickness | 50–200 nm | SiO₂ |
Thickness | ≥ 300 nm | — |
Thickness | ≥ 200 nm | — |
GaN MOSFET 100 (first embodiment, described in detail)
gate insulating film
AlGaN layer
AlxGa₁-xN
gate insulating film (silicon oxide)
SiO₂
gate electrode (p-type or n-type polysilicon)
thickness of low impurity concentration region (channel region) of p-type GaN layer | 0.5–2 µm | GaN |
thickness of high impurity concentration region (channel contact region) of p-type GaN layer | 50–300 nm | GaN |
trench depth | 1–2 µm | — |
gate insulating film (SiO2) thickness | 50–200 nm | SiO₂ |
Thickness | ≥ 300 nm | — |
Thickness | ≥ 200 nm | — |