Patent
US 9,412,815SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES
Phaedon Avouris
US
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Patent
Atlas literature
Patent
US 9,412,815Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1-20 are a series of views illustrating a method of forming carbon nanotubes on a semiconductor device according to an exemplary process flow, in which:
Figure 2 illustrates formation of a graphene layer atop the starting substrate of
Figure 3 illustrates formation of a masking layer atop the graphene layer shown in
Figure 4 illustrates a cross-sectional view of the semiconductor device shown in
Figure 5 is a top view of the semiconductor device shown in
Figure 6 is a top view of the semiconductor device shown in
Figure 7 is a cross-sectional view of the semiconductor device illustrated in
Figure 8 is a top view of the semiconductor device shown in
Figure 9 is a cross-sectional view of the semiconductor device illustrated in
Figure 10 is a top view of the semiconductor device illustrated in
Figure 11 illustrates the semiconductor device shown in
Figure 12 illustrates the semiconductor device of
Figure 13 is a top view of the semiconductor device of
Figure 14 is a top view of the semiconductor device of
Figure 15 illustrates the semiconductor device of
Figure 16 is a top view of the semiconductor device of
Figure 17 illustrates the semiconductor device of claim 15 following removal of the graphene electrodes to expose the underlying substrate;
Figure 18 is a top view of the semiconductor device illustrated in
Figure 19 illustrates the semiconductor device of
Figure 20 is a top view of the semiconductor device illustrated in
Figures 21-24 are a series of views illustrating a semiconductor device including a graphene electrode network to arrange carbon nanotubes, in which:
Figure 22 is a top view of the semiconductor device shown in
Figure 23 is a top view of the semiconductor device illustrated in
Figure 24 is a top view of the semiconductor device illustrated in
Figure 25 is a flow diagram illustrating a method of forming carbon nanotubes on a semiconductor device according to an embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having at least one electrically insulating portion; a first graphene electrode fo rm ed on a surface defined by a location area of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode; and a second graphene electrode fo rm ed on the surface of the substrate such that the electrically insulating portion is interposed between the bulk portion of the substrate and the second graphene electrode, the second graphene electrode disposed opposite the first graphene electrode to define an exposed substrate area therebetween, wherein the first graphene electrode is configured to receive a voltage source and the second graphene electrode is configured to receive a ground source, the voltage and ground sources inducing an electric field including a plurality of field lines, the electric field forcing the at least one carbon nanotube to the exposed substrate area and aligning the at least one carbon nanotube in a direction parallel to the field lines, and wherein the first and second graphene electrodes each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, and wherein e ach teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner odge peak of the a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner edge of peak of the first a respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 1, further comprising at least one carbon nanotube deposited on the surface of the substrate.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 2 of 7 Application Serial No: 14/496,048 In Reply to Office Action dated: canceled
A semiconductor device, comprising: a substrate wafer configured to insulate electrical current from flowing therethrough; a graphene electrode network including first and second electrode branches separated from one another by an exposed portion of the substrate wafer, the first and second electrode branches extending along the substrate in direction parallel to one another, the first electrode branch configured to receive a voltage source and the second electrode branch configured to receive a ground source; and a plurality of carbon nanotube arrays arranged between the first and second electrode branches, the plurality of carbon nanotube arrays including a plurality of carbon nanotubes aligned perpendicular to the first and second electrode branches in response to an electric field induced by applying the voltage and ground sources, wherein the first and second graphene electrode branches each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, and wherein each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner peak edge of theo f a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner odge peak of the a first respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 6, wherein the first and second electrode braches extend in a plurality of different directions such that the plurality of carbon nanotube arrays are aligned differently according to the directions of the first and second electrode branches.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 4 of 7 canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene electrodes and carbon nanotube array
semiconductor device with graphene electrode network and carbon nanotube arrays
Materials described outside the worked examples.
graphene
carbon nanotube
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,815Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1-20 are a series of views illustrating a method of forming carbon nanotubes on a semiconductor device according to an exemplary process flow, in which:
Figure 2 illustrates formation of a graphene layer atop the starting substrate of
Figure 3 illustrates formation of a masking layer atop the graphene layer shown in
Figure 4 illustrates a cross-sectional view of the semiconductor device shown in
Figure 5 is a top view of the semiconductor device shown in
Figure 6 is a top view of the semiconductor device shown in
Figure 7 is a cross-sectional view of the semiconductor device illustrated in
Figure 8 is a top view of the semiconductor device shown in
Figure 9 is a cross-sectional view of the semiconductor device illustrated in
Figure 10 is a top view of the semiconductor device illustrated in
Figure 11 illustrates the semiconductor device shown in
Figure 12 illustrates the semiconductor device of
Figure 13 is a top view of the semiconductor device of
Figure 14 is a top view of the semiconductor device of
Figure 15 illustrates the semiconductor device of
Figure 16 is a top view of the semiconductor device of
Figure 17 illustrates the semiconductor device of claim 15 following removal of the graphene electrodes to expose the underlying substrate;
Figure 18 is a top view of the semiconductor device illustrated in
Figure 19 illustrates the semiconductor device of
Figure 20 is a top view of the semiconductor device illustrated in
Figures 21-24 are a series of views illustrating a semiconductor device including a graphene electrode network to arrange carbon nanotubes, in which:
Figure 22 is a top view of the semiconductor device shown in
Figure 23 is a top view of the semiconductor device illustrated in
Figure 24 is a top view of the semiconductor device illustrated in
Figure 25 is a flow diagram illustrating a method of forming carbon nanotubes on a semiconductor device according to an embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having at least one electrically insulating portion; a first graphene electrode fo rm ed on a surface defined by a location area of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode; and a second graphene electrode fo rm ed on the surface of the substrate such that the electrically insulating portion is interposed between the bulk portion of the substrate and the second graphene electrode, the second graphene electrode disposed opposite the first graphene electrode to define an exposed substrate area therebetween, wherein the first graphene electrode is configured to receive a voltage source and the second graphene electrode is configured to receive a ground source, the voltage and ground sources inducing an electric field including a plurality of field lines, the electric field forcing the at least one carbon nanotube to the exposed substrate area and aligning the at least one carbon nanotube in a direction parallel to the field lines, and wherein the first and second graphene electrodes each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, and wherein e ach teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner odge peak of the a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner edge of peak of the first a respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 1, further comprising at least one carbon nanotube deposited on the surface of the substrate.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 2 of 7 Application Serial No: 14/496,048 In Reply to Office Action dated: canceled
A semiconductor device, comprising: a substrate wafer configured to insulate electrical current from flowing therethrough; a graphene electrode network including first and second electrode branches separated from one another by an exposed portion of the substrate wafer, the first and second electrode branches extending along the substrate in direction parallel to one another, the first electrode branch configured to receive a voltage source and the second electrode branch configured to receive a ground source; and a plurality of carbon nanotube arrays arranged between the first and second electrode branches, the plurality of carbon nanotube arrays including a plurality of carbon nanotubes aligned perpendicular to the first and second electrode branches in response to an electric field induced by applying the voltage and ground sources, wherein the first and second graphene electrode branches each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, and wherein each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner peak edge of theo f a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner odge peak of the a first respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 6, wherein the first and second electrode braches extend in a plurality of different directions such that the plurality of carbon nanotube arrays are aligned differently according to the directions of the first and second electrode branches.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 4 of 7 canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene electrodes and carbon nanotube array
semiconductor device with graphene electrode network and carbon nanotube arrays
Materials described outside the worked examples.
graphene
carbon nanotube
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,815Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1-20 are a series of views illustrating a method of forming carbon nanotubes on a semiconductor device according to an exemplary process flow, in which:
Figure 2 illustrates formation of a graphene layer atop the starting substrate of
Figure 3 illustrates formation of a masking layer atop the graphene layer shown in
Figure 4 illustrates a cross-sectional view of the semiconductor device shown in
Figure 5 is a top view of the semiconductor device shown in
Figure 6 is a top view of the semiconductor device shown in
Figure 7 is a cross-sectional view of the semiconductor device illustrated in
Figure 8 is a top view of the semiconductor device shown in
Figure 9 is a cross-sectional view of the semiconductor device illustrated in
Figure 10 is a top view of the semiconductor device illustrated in
Figure 11 illustrates the semiconductor device shown in
Figure 12 illustrates the semiconductor device of
Figure 13 is a top view of the semiconductor device of
Figure 14 is a top view of the semiconductor device of
Figure 15 illustrates the semiconductor device of
Figure 16 is a top view of the semiconductor device of
Figure 17 illustrates the semiconductor device of claim 15 following removal of the graphene electrodes to expose the underlying substrate;
Figure 18 is a top view of the semiconductor device illustrated in
Figure 19 illustrates the semiconductor device of
Figure 20 is a top view of the semiconductor device illustrated in
Figures 21-24 are a series of views illustrating a semiconductor device including a graphene electrode network to arrange carbon nanotubes, in which:
Figure 22 is a top view of the semiconductor device shown in
Figure 23 is a top view of the semiconductor device illustrated in
Figure 24 is a top view of the semiconductor device illustrated in
Figure 25 is a flow diagram illustrating a method of forming carbon nanotubes on a semiconductor device according to an embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having at least one electrically insulating portion; a first graphene electrode fo rm ed on a surface defined by a location area of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode; and a second graphene electrode fo rm ed on the surface of the substrate such that the electrically insulating portion is interposed between the bulk portion of the substrate and the second graphene electrode, the second graphene electrode disposed opposite the first graphene electrode to define an exposed substrate area therebetween, wherein the first graphene electrode is configured to receive a voltage source and the second graphene electrode is configured to receive a ground source, the voltage and ground sources inducing an electric field including a plurality of field lines, the electric field forcing the at least one carbon nanotube to the exposed substrate area and aligning the at least one carbon nanotube in a direction parallel to the field lines, and wherein the first and second graphene electrodes each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, and wherein e ach teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner odge peak of the a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner edge of peak of the first a respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 1, further comprising at least one carbon nanotube deposited on the surface of the substrate.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 2 of 7 Application Serial No: 14/496,048 In Reply to Office Action dated: canceled
A semiconductor device, comprising: a substrate wafer configured to insulate electrical current from flowing therethrough; a graphene electrode network including first and second electrode branches separated from one another by an exposed portion of the substrate wafer, the first and second electrode branches extending along the substrate in direction parallel to one another, the first electrode branch configured to receive a voltage source and the second electrode branch configured to receive a ground source; and a plurality of carbon nanotube arrays arranged between the first and second electrode branches, the plurality of carbon nanotube arrays including a plurality of carbon nanotubes aligned perpendicular to the first and second electrode branches in response to an electric field induced by applying the voltage and ground sources, wherein the first and second graphene electrode branches each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, and wherein each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner peak edge of theo f a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner odge peak of the a first respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 6, wherein the first and second electrode braches extend in a plurality of different directions such that the plurality of carbon nanotube arrays are aligned differently according to the directions of the first and second electrode branches.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 4 of 7 canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene electrodes and carbon nanotube array
semiconductor device with graphene electrode network and carbon nanotube arrays
Materials described outside the worked examples.
graphene
carbon nanotube
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,815Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1-20 are a series of views illustrating a method of forming carbon nanotubes on a semiconductor device according to an exemplary process flow, in which:
Figure 2 illustrates formation of a graphene layer atop the starting substrate of
Figure 3 illustrates formation of a masking layer atop the graphene layer shown in
Figure 4 illustrates a cross-sectional view of the semiconductor device shown in
Figure 5 is a top view of the semiconductor device shown in
Figure 6 is a top view of the semiconductor device shown in
Figure 7 is a cross-sectional view of the semiconductor device illustrated in
Figure 8 is a top view of the semiconductor device shown in
Figure 9 is a cross-sectional view of the semiconductor device illustrated in
Figure 10 is a top view of the semiconductor device illustrated in
Figure 11 illustrates the semiconductor device shown in
Figure 12 illustrates the semiconductor device of
Figure 13 is a top view of the semiconductor device of
Figure 14 is a top view of the semiconductor device of
Figure 15 illustrates the semiconductor device of
Figure 16 is a top view of the semiconductor device of
Figure 17 illustrates the semiconductor device of claim 15 following removal of the graphene electrodes to expose the underlying substrate;
Figure 18 is a top view of the semiconductor device illustrated in
Figure 19 illustrates the semiconductor device of
Figure 20 is a top view of the semiconductor device illustrated in
Figures 21-24 are a series of views illustrating a semiconductor device including a graphene electrode network to arrange carbon nanotubes, in which:
Figure 22 is a top view of the semiconductor device shown in
Figure 23 is a top view of the semiconductor device illustrated in
Figure 24 is a top view of the semiconductor device illustrated in
Figure 25 is a flow diagram illustrating a method of forming carbon nanotubes on a semiconductor device according to an embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having at least one electrically insulating portion; a first graphene electrode fo rm ed on a surface defined by a location area of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode; and a second graphene electrode fo rm ed on the surface of the substrate such that the electrically insulating portion is interposed between the bulk portion of the substrate and the second graphene electrode, the second graphene electrode disposed opposite the first graphene electrode to define an exposed substrate area therebetween, wherein the first graphene electrode is configured to receive a voltage source and the second graphene electrode is configured to receive a ground source, the voltage and ground sources inducing an electric field including a plurality of field lines, the electric field forcing the at least one carbon nanotube to the exposed substrate area and aligning the at least one carbon nanotube in a direction parallel to the field lines, and wherein the first and second graphene electrodes each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, and wherein e ach teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner odge peak of the a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner edge of peak of the first a respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 1, further comprising at least one carbon nanotube deposited on the surface of the substrate.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 2 of 7 Application Serial No: 14/496,048 In Reply to Office Action dated: canceled
A semiconductor device, comprising: a substrate wafer configured to insulate electrical current from flowing therethrough; a graphene electrode network including first and second electrode branches separated from one another by an exposed portion of the substrate wafer, the first and second electrode branches extending along the substrate in direction parallel to one another, the first electrode branch configured to receive a voltage source and the second electrode branch configured to receive a ground source; and a plurality of carbon nanotube arrays arranged between the first and second electrode branches, the plurality of carbon nanotube arrays including a plurality of carbon nanotubes aligned perpendicular to the first and second electrode branches in response to an electric field induced by applying the voltage and ground sources, wherein the first and second graphene electrode branches each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth- like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, and wherein each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first inner peak edge of theo f a respective first teeth-like portion and a second end of each carbon nanotube contacts a second inner odge peak of the a first respective second teeth-like portion without suspending the carbon nanotube array above the carbon nanotube contacts.
The semiconductor device of claim 6, wherein the first and second electrode braches extend in a plurality of different directions such that the plurality of carbon nanotube arrays are aligned differently according to the directions of the first and second electrode branches.
Attorney Docket No. Y O R₉₂₀₁₂₀₈₈₂US₂ Page 4 of 7 canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene electrodes and carbon nanotube array
semiconductor device with graphene electrode network and carbon nanotube arrays
Materials described outside the worked examples.
graphene
carbon nanotube
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 nm | — |
Related documents with shared materials, methods, properties, or citations.
electrically insulating substrate material
silicon
Si
silicon carbide
SiC
silicon dioxide
SiO₂
poly(methyl methacrylate)
hydrogen silsesquioxane
electrically insulating substrate material
silicon
Si
silicon carbide
SiC
silicon dioxide
SiO₂
poly(methyl methacrylate)
hydrogen silsesquioxane
electrically insulating substrate material
silicon
Si
silicon carbide
SiC
silicon dioxide
SiO₂
poly(methyl methacrylate)
hydrogen silsesquioxane
electrically insulating substrate material
silicon
Si
silicon carbide
SiC
silicon dioxide
SiO₂
poly(methyl methacrylate)
hydrogen silsesquioxane