Patent
US 11,258,444DEVICES AND METHODS FOR HIGH-EFFICIENCY POWER SWITCHING WITH CASCODE GAN
Indra Prakash
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,258,444Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a functional block diagram of an uninterruptible power supply in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional Cascode GaN power switching device;
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
FIG. 4A is a functional block diagram of a power switching circuit in accordance with one embodiment of the present invention;
FIG. 5 B is a schematic diagram a power switching device in accordance with one embodiment of the present invention; and
FIG. 6 is a schematic diagram of a power switching device in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power switching circuit, comprising: a first terminal; a second te rm inal; a third terminal; and a plurality of switching devices, each switching device having: a first transistor having a first gate, a first source, and a first drain; a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source; and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a second switching device of the plurality of switching devices is coupled between the second terminal and the third terminal, and wherein each switching device of the plurality of switching devices is configured such that the first gate is coupled to the second source. Currently amended
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the second source and a cathode coupled to the first drain. Original
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the first gate and a cathode coupled to the first source. Original
The power switching circuit of claim 1, wherein the third terminal is configured to be coupled to an AC power source, the first terminal and the second terminal are configured to be coupled to a DC bus, and the power switching circuit is configured to be operated as a power converter in a UPS. Original
The power switching circuit of claim 1, wherein the first terminal and the second terminal are configured to be coupled to a DC bus, the third terminal is configured to be coupled to a load, and the power switching circuit is configured to operate as a power inverter in a UPS. Original
The power switching circuit of claim 1, wherein the second terminal is coupled to a ground connection. Original
The power switching circuit of claim 1, wherein a third switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a fourth switching device of the plurality of switching devices is coupled between the second terminal and the third terminal. Original
Canceled
The power switching circuit of claim [[4]] 1, wherein the first transistor of each switching device is a depletion mode transistor and the second transistor of each switching device is an enhancement mode transistor. Currently amended
The power switching circuit of claim 5, wherein the first transistor of each switching device is a GaN HEMT and the second transistor of each switching device is a low-voltage FET. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having an anode coupled to the second source and a cathode coupled to the first drain, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; diverting at least a portion of the transition cu rr ent through the unipolar diode to the first drain such that a transition voltage applied across the first gate and the first source does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 15, wherein diverting the transition current through the unipolar diode prevents the transition voltage from exceeding the degradation threshold of the first transistor by reducing a forward recovery voltage of the bipolar body diode of the second transistor. Original
The method of claim 15, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the power switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, and a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having a cathode coupled to the first source and an anode coupled to first, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; regulating a transition voltage applied across the first gate and the first source via the unipolar diode such that the transition voltage does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 18, wherein regulating the transition voltage via the unipolar diode reduces a forward recovery voltage of the bipolar body diode of the second transistor to prevent the transition voltage from exceeding the degradation threshold of the first transistor. Original
The method of claim 18, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
Layer stacks claimed or described, ordered top of device to substrate.
cascode GaN power switching device
Materials described outside the worked examples.
GaN HEMT
Schottky Barrier diode
low-voltage FET
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEMS AND METHODS FOR A RADIO FREQUENCY TRANSMITTER WITH IMPROVED LINEARITY AND POWER OUT UTILIZING PRE-DISTORTION AND A GAN (GALLIUM NITRIDE) POWER AMPLIFIER DEVICE
ANSWER CLASSIFIER AND REPRESENTATION GENERATOR FOR QUESTION-ANSWERING SYSTEM USING GAN, AND COMPUTER PROGRAM FOR TRAINING THE REPRESENTATION GENERATOR
Patent
Atlas literature
Patent
US 11,258,444Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a functional block diagram of an uninterruptible power supply in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional Cascode GaN power switching device;
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
FIG. 4A is a functional block diagram of a power switching circuit in accordance with one embodiment of the present invention;
FIG. 5 B is a schematic diagram a power switching device in accordance with one embodiment of the present invention; and
FIG. 6 is a schematic diagram of a power switching device in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power switching circuit, comprising: a first terminal; a second te rm inal; a third terminal; and a plurality of switching devices, each switching device having: a first transistor having a first gate, a first source, and a first drain; a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source; and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a second switching device of the plurality of switching devices is coupled between the second terminal and the third terminal, and wherein each switching device of the plurality of switching devices is configured such that the first gate is coupled to the second source. Currently amended
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the second source and a cathode coupled to the first drain. Original
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the first gate and a cathode coupled to the first source. Original
The power switching circuit of claim 1, wherein the third terminal is configured to be coupled to an AC power source, the first terminal and the second terminal are configured to be coupled to a DC bus, and the power switching circuit is configured to be operated as a power converter in a UPS. Original
The power switching circuit of claim 1, wherein the first terminal and the second terminal are configured to be coupled to a DC bus, the third terminal is configured to be coupled to a load, and the power switching circuit is configured to operate as a power inverter in a UPS. Original
The power switching circuit of claim 1, wherein the second terminal is coupled to a ground connection. Original
The power switching circuit of claim 1, wherein a third switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a fourth switching device of the plurality of switching devices is coupled between the second terminal and the third terminal. Original
Canceled
The power switching circuit of claim [[4]] 1, wherein the first transistor of each switching device is a depletion mode transistor and the second transistor of each switching device is an enhancement mode transistor. Currently amended
The power switching circuit of claim 5, wherein the first transistor of each switching device is a GaN HEMT and the second transistor of each switching device is a low-voltage FET. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having an anode coupled to the second source and a cathode coupled to the first drain, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; diverting at least a portion of the transition cu rr ent through the unipolar diode to the first drain such that a transition voltage applied across the first gate and the first source does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 15, wherein diverting the transition current through the unipolar diode prevents the transition voltage from exceeding the degradation threshold of the first transistor by reducing a forward recovery voltage of the bipolar body diode of the second transistor. Original
The method of claim 15, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the power switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, and a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having a cathode coupled to the first source and an anode coupled to first, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; regulating a transition voltage applied across the first gate and the first source via the unipolar diode such that the transition voltage does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 18, wherein regulating the transition voltage via the unipolar diode reduces a forward recovery voltage of the bipolar body diode of the second transistor to prevent the transition voltage from exceeding the degradation threshold of the first transistor. Original
The method of claim 18, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
Layer stacks claimed or described, ordered top of device to substrate.
cascode GaN power switching device
Materials described outside the worked examples.
GaN HEMT
Schottky Barrier diode
low-voltage FET
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEMS AND METHODS FOR A RADIO FREQUENCY TRANSMITTER WITH IMPROVED LINEARITY AND POWER OUT UTILIZING PRE-DISTORTION AND A GAN (GALLIUM NITRIDE) POWER AMPLIFIER DEVICE
ANSWER CLASSIFIER AND REPRESENTATION GENERATOR FOR QUESTION-ANSWERING SYSTEM USING GAN, AND COMPUTER PROGRAM FOR TRAINING THE REPRESENTATION GENERATOR
Patent
Atlas literature
Patent
US 11,258,444Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a functional block diagram of an uninterruptible power supply in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional Cascode GaN power switching device;
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
FIG. 4A is a functional block diagram of a power switching circuit in accordance with one embodiment of the present invention;
FIG. 5 B is a schematic diagram a power switching device in accordance with one embodiment of the present invention; and
FIG. 6 is a schematic diagram of a power switching device in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power switching circuit, comprising: a first terminal; a second te rm inal; a third terminal; and a plurality of switching devices, each switching device having: a first transistor having a first gate, a first source, and a first drain; a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source; and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a second switching device of the plurality of switching devices is coupled between the second terminal and the third terminal, and wherein each switching device of the plurality of switching devices is configured such that the first gate is coupled to the second source. Currently amended
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the second source and a cathode coupled to the first drain. Original
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the first gate and a cathode coupled to the first source. Original
The power switching circuit of claim 1, wherein the third terminal is configured to be coupled to an AC power source, the first terminal and the second terminal are configured to be coupled to a DC bus, and the power switching circuit is configured to be operated as a power converter in a UPS. Original
The power switching circuit of claim 1, wherein the first terminal and the second terminal are configured to be coupled to a DC bus, the third terminal is configured to be coupled to a load, and the power switching circuit is configured to operate as a power inverter in a UPS. Original
The power switching circuit of claim 1, wherein the second terminal is coupled to a ground connection. Original
The power switching circuit of claim 1, wherein a third switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a fourth switching device of the plurality of switching devices is coupled between the second terminal and the third terminal. Original
Canceled
The power switching circuit of claim [[4]] 1, wherein the first transistor of each switching device is a depletion mode transistor and the second transistor of each switching device is an enhancement mode transistor. Currently amended
The power switching circuit of claim 5, wherein the first transistor of each switching device is a GaN HEMT and the second transistor of each switching device is a low-voltage FET. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having an anode coupled to the second source and a cathode coupled to the first drain, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; diverting at least a portion of the transition cu rr ent through the unipolar diode to the first drain such that a transition voltage applied across the first gate and the first source does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 15, wherein diverting the transition current through the unipolar diode prevents the transition voltage from exceeding the degradation threshold of the first transistor by reducing a forward recovery voltage of the bipolar body diode of the second transistor. Original
The method of claim 15, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the power switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, and a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having a cathode coupled to the first source and an anode coupled to first, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; regulating a transition voltage applied across the first gate and the first source via the unipolar diode such that the transition voltage does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 18, wherein regulating the transition voltage via the unipolar diode reduces a forward recovery voltage of the bipolar body diode of the second transistor to prevent the transition voltage from exceeding the degradation threshold of the first transistor. Original
The method of claim 18, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
Layer stacks claimed or described, ordered top of device to substrate.
cascode GaN power switching device
Materials described outside the worked examples.
GaN HEMT
Schottky Barrier diode
low-voltage FET
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEMS AND METHODS FOR A RADIO FREQUENCY TRANSMITTER WITH IMPROVED LINEARITY AND POWER OUT UTILIZING PRE-DISTORTION AND A GAN (GALLIUM NITRIDE) POWER AMPLIFIER DEVICE
ANSWER CLASSIFIER AND REPRESENTATION GENERATOR FOR QUESTION-ANSWERING SYSTEM USING GAN, AND COMPUTER PROGRAM FOR TRAINING THE REPRESENTATION GENERATOR
Patent
Atlas literature
Patent
US 11,258,444Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a functional block diagram of an uninterruptible power supply in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of a conventional Cascode GaN power switching device;
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
FIG. 4A is a functional block diagram of a power switching circuit in accordance with one embodiment of the present invention;
FIG. 5 B is a schematic diagram a power switching device in accordance with one embodiment of the present invention; and
FIG. 6 is a schematic diagram of a power switching device in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power switching circuit, comprising: a first terminal; a second te rm inal; a third terminal; and a plurality of switching devices, each switching device having: a first transistor having a first gate, a first source, and a first drain; a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source; and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a second switching device of the plurality of switching devices is coupled between the second terminal and the third terminal, and wherein each switching device of the plurality of switching devices is configured such that the first gate is coupled to the second source. Currently amended
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the second source and a cathode coupled to the first drain. Original
The power switching circuit of claim 1, wherein the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the first gate and a cathode coupled to the first source. Original
The power switching circuit of claim 1, wherein the third terminal is configured to be coupled to an AC power source, the first terminal and the second terminal are configured to be coupled to a DC bus, and the power switching circuit is configured to be operated as a power converter in a UPS. Original
The power switching circuit of claim 1, wherein the first terminal and the second terminal are configured to be coupled to a DC bus, the third terminal is configured to be coupled to a load, and the power switching circuit is configured to operate as a power inverter in a UPS. Original
The power switching circuit of claim 1, wherein the second terminal is coupled to a ground connection. Original
The power switching circuit of claim 1, wherein a third switching device of the plurality of switching devices is coupled between the first terminal and the third terminal and a fourth switching device of the plurality of switching devices is coupled between the second terminal and the third terminal. Original
Canceled
The power switching circuit of claim [[4]] 1, wherein the first transistor of each switching device is a depletion mode transistor and the second transistor of each switching device is an enhancement mode transistor. Currently amended
The power switching circuit of claim 5, wherein the first transistor of each switching device is a GaN HEMT and the second transistor of each switching device is a low-voltage FET. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having an anode coupled to the second source and a cathode coupled to the first drain, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; diverting at least a portion of the transition cu rr ent through the unipolar diode to the first drain such that a transition voltage applied across the first gate and the first source does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 15, wherein diverting the transition current through the unipolar diode prevents the transition voltage from exceeding the degradation threshold of the first transistor by reducing a forward recovery voltage of the bipolar body diode of the second transistor. Original
The method of claim 15, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
A method for maintaining operational efficiency of a switching device in a power switching circuit, the power switching device having a first transistor and a second transistor, the first transistor having a first gate, a first source, and a first drain, the second transistor having a second gate, a second source coupled to the first gate, and a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode having a cathode coupled to the first source and an anode coupled to first, wherein the method comprises: receiving a transition current at the second source during a transition period of the power switching circuit; regulating a transition voltage applied across the first gate and the first source via the unipolar diode such that the transition voltage does not exceed a degradation threshold of the first transistor; determining that the transition period of the power switching circuit has ended; and enabling, in response to a determination that the transition period has ended, the second transistor such that an operational current applied to the first drain is switched through the first transistor and the second transistor to the second source. Currently amended
The method of claim 18, wherein regulating the transition voltage via the unipolar diode reduces a forward recovery voltage of the bipolar body diode of the second transistor to prevent the transition voltage from exceeding the degradation threshold of the first transistor. Original
The method of claim 18, wherein the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode. Original
Layer stacks claimed or described, ordered top of device to substrate.
cascode GaN power switching device
Materials described outside the worked examples.
GaN HEMT
Schottky Barrier diode
low-voltage FET
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3B is graph illustrating voltage and current waveforms associated with the half- bridge inverter circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≤ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEMS AND METHODS FOR A RADIO FREQUENCY TRANSMITTER WITH IMPROVED LINEARITY AND POWER OUT UTILIZING PRE-DISTORTION AND A GAN (GALLIUM NITRIDE) POWER AMPLIFIER DEVICE
ANSWER CLASSIFIER AND REPRESENTATION GENERATOR FOR QUESTION-ANSWERING SYSTEM USING GAN, AND COMPUTER PROGRAM FOR TRAINING THE REPRESENTATION GENERATOR