Patent
US 10,455,529MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) AMPLIFIER CIRCUIT
Mihai SANDULEANU
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,455,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example Doherty amplifier architecture including a main power amplifier (PA) and auxiliary PA. [0006]
FIG. 2 shows a radio frequency (RF) PA architecture using a polar modulation technique. [0007]
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
FIG. 4 shows an example approach for performing out-phasing of an RF signal. [0009]
FIG. 5 shows an example RF transmitter architecture in accordance with embodiments of the present disclosure. [0010]
FIG. 6B shows an example timing diagram and digital logic for performing MUX-based digital upconverting of outphased IF signals, in accordance with an …
FIG. 7 shows a graph that depicts the output spectrum of a simulated 802.1 1 a signal relative to a spectral mask after performing a MUX-based digital …
FIG. 8A showns an example system diagram of an output stage and an antenna driving stage suitable for use in the RF transmitter architecture of
FIG. 9B is a timing diagram showing drain voltage relative to drain currrent over time (t) during operation of the amplifier circuit of
FIG. 10 shows a schematic view of an example inverse Class-D amplifier circuit, in accordance with an embodiment of the present disclosure. [0019]
FIG. 11 illustrates a plurality of inverter circuits suitable for driving the amplifier circuit of
FIG. 12 shows a schematic view of the example inverse Class-D switch mode amplifier circuit of
FIG. 13 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 14 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The transmitter system of claim 1, wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.7.svg 0.15 3.7 Black and white Title: MULTISTANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) Original
The transmitter system of claim 1, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. Original
The transmitter system of claim 1, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Original
The transmitter system of claim 1, wherein the upper switching device and/or the lower switching device comprise high-voltage GaN high electron mobility transistor (HEMT) devices. Original
The transmitter system of claim 1, further comprising the antenna driving circuit, and wherein the antenna driving circuit is implemented on a different chip than the GaN PA circuit. Original
8-9. Canceled
Canceled
The transmitter system of claim 1, further comprising a digital upconvert stage, the digital upconvert stage comprising: an intermediate frequency (IF) processor for receiving a first signal (I (t)) representing an in-phase component of an output waveform and a second signal (Q(t)) representing the quadrature component of the output waveform, and outputting a first and second set of outphased IF signals; and digital upconvert circuitry to receive the first and second set of outphased IF signals and digitally upconvert the first and second set of outphased IF signals to provide the RF signal for driving the GaN PA circuit. Original
The transmitter system of claim 10, wherein the digital upconvert stage is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC). Original
The transmitter system of claim 10, wherein the digital upconvert stage and the output stage are electrically coupled via a 50 ohm terminated transmission line. Original
A method for digitally upconverting an intermediate frequency (IF) signal, the method comprising: receiving a first outphased signal (V I) and a second outphased signal (V Q), multiplying the first outphased signal (V I) with a first multi-level digital clock signal (L O 1 (t)) to provide a first digitally upconverted signal at a first carrier frequency; and multiplying the second outphased signal (V Q) with a second multi-level digital clock signal (LO I (q)) to provide a second digitally upconverted signal at the first carrier frequency) wherein the first and second multi-level digital clock signals each comprise signal levels of-1V, O V, and +1V. Currently amended
The method of claim 13, further comprising summing the first and second outphased signals to derive an RF signal to provide to a PA stage based on the following equation: SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.8.svg 0.18 2.43 Black and white Original
Canceled
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) when operating at a frequency of substantially 1 Gigahertz (GHz) and an output power substantially equal to 10 Watts (W). Currently amended
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Currently amended
The transmitter system [[device]]of claim 21, [[16,]]wherein the upconvert circuit is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) and is electrically coupled to the output stage via a 50 ohm terminated transmission line. Currently amended
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the upper switching device of the first cascode transistor SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.9.svg 0.16 2.9 Black and white Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) New
The transmitter system of claim 21, further comprising an upconvert circuit having a plurality of stages to digitally upconvert outphased IF signals and provide an upconverted outphased digital RF signal; and wherein the output stage further comprises: an amplification circuit to receive the outphased digital RF signal and generate a driving signal based on outphased digital RF signal; and a driving circuit comprising an inverter circuit to drive said GaN PA circuit based on the driving signal. New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration. New
The transmitter system of claim 23, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. New
The transmitter system of claim 23, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W). New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; wherein the output stage further comprises a two-stage driver circuit, the two-stage driver circuit comprising: a first stage to receive a digital outphased intermediate frequency (IF) signal and generate a driving signal based on the digital outphased IF signal; a second stage comprising an inverter circuit to couple to the input of the GaN PA circuit and drive the GaN PA circuit based on the driving signal; and wherein the driving signal provides a 0 to V DD s wing s of the first cascode transistor arrangement. New
The transmitter system of claim 26, wherein driving circuit are implemented on the same chip. uffi c ient to switch on the lower switching device the two-stage driver circuit and the GaN PA New
Layer stacks claimed or described, ordered top of device to substrate.
GaN PA circuit with Modified CMCD configuration and first cascode transistor arrangement
GaN high electron mobility transistor (HEMT) device
GaN PA circuit with inverse CMCD configuration (first and second cascode arrangements)
Materials described outside the worked examples.
Gallium Nitride
GaN
complementary metal-oxide semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak drain efficiency at 1 GHz, 10 W output | 80–85 | GaN |
peak drain efficiency at 1 GHz, 10 W output (abstract/description) | ≥ 85 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,455,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example Doherty amplifier architecture including a main power amplifier (PA) and auxiliary PA. [0006]
FIG. 2 shows a radio frequency (RF) PA architecture using a polar modulation technique. [0007]
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
FIG. 4 shows an example approach for performing out-phasing of an RF signal. [0009]
FIG. 5 shows an example RF transmitter architecture in accordance with embodiments of the present disclosure. [0010]
FIG. 6B shows an example timing diagram and digital logic for performing MUX-based digital upconverting of outphased IF signals, in accordance with an …
FIG. 7 shows a graph that depicts the output spectrum of a simulated 802.1 1 a signal relative to a spectral mask after performing a MUX-based digital …
FIG. 8A showns an example system diagram of an output stage and an antenna driving stage suitable for use in the RF transmitter architecture of
FIG. 9B is a timing diagram showing drain voltage relative to drain currrent over time (t) during operation of the amplifier circuit of
FIG. 10 shows a schematic view of an example inverse Class-D amplifier circuit, in accordance with an embodiment of the present disclosure. [0019]
FIG. 11 illustrates a plurality of inverter circuits suitable for driving the amplifier circuit of
FIG. 12 shows a schematic view of the example inverse Class-D switch mode amplifier circuit of
FIG. 13 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 14 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The transmitter system of claim 1, wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.7.svg 0.15 3.7 Black and white Title: MULTISTANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) Original
The transmitter system of claim 1, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. Original
The transmitter system of claim 1, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Original
The transmitter system of claim 1, wherein the upper switching device and/or the lower switching device comprise high-voltage GaN high electron mobility transistor (HEMT) devices. Original
The transmitter system of claim 1, further comprising the antenna driving circuit, and wherein the antenna driving circuit is implemented on a different chip than the GaN PA circuit. Original
8-9. Canceled
Canceled
The transmitter system of claim 1, further comprising a digital upconvert stage, the digital upconvert stage comprising: an intermediate frequency (IF) processor for receiving a first signal (I (t)) representing an in-phase component of an output waveform and a second signal (Q(t)) representing the quadrature component of the output waveform, and outputting a first and second set of outphased IF signals; and digital upconvert circuitry to receive the first and second set of outphased IF signals and digitally upconvert the first and second set of outphased IF signals to provide the RF signal for driving the GaN PA circuit. Original
The transmitter system of claim 10, wherein the digital upconvert stage is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC). Original
The transmitter system of claim 10, wherein the digital upconvert stage and the output stage are electrically coupled via a 50 ohm terminated transmission line. Original
A method for digitally upconverting an intermediate frequency (IF) signal, the method comprising: receiving a first outphased signal (V I) and a second outphased signal (V Q), multiplying the first outphased signal (V I) with a first multi-level digital clock signal (L O 1 (t)) to provide a first digitally upconverted signal at a first carrier frequency; and multiplying the second outphased signal (V Q) with a second multi-level digital clock signal (LO I (q)) to provide a second digitally upconverted signal at the first carrier frequency) wherein the first and second multi-level digital clock signals each comprise signal levels of-1V, O V, and +1V. Currently amended
The method of claim 13, further comprising summing the first and second outphased signals to derive an RF signal to provide to a PA stage based on the following equation: SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.8.svg 0.18 2.43 Black and white Original
Canceled
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) when operating at a frequency of substantially 1 Gigahertz (GHz) and an output power substantially equal to 10 Watts (W). Currently amended
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Currently amended
The transmitter system [[device]]of claim 21, [[16,]]wherein the upconvert circuit is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) and is electrically coupled to the output stage via a 50 ohm terminated transmission line. Currently amended
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the upper switching device of the first cascode transistor SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.9.svg 0.16 2.9 Black and white Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) New
The transmitter system of claim 21, further comprising an upconvert circuit having a plurality of stages to digitally upconvert outphased IF signals and provide an upconverted outphased digital RF signal; and wherein the output stage further comprises: an amplification circuit to receive the outphased digital RF signal and generate a driving signal based on outphased digital RF signal; and a driving circuit comprising an inverter circuit to drive said GaN PA circuit based on the driving signal. New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration. New
The transmitter system of claim 23, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. New
The transmitter system of claim 23, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W). New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; wherein the output stage further comprises a two-stage driver circuit, the two-stage driver circuit comprising: a first stage to receive a digital outphased intermediate frequency (IF) signal and generate a driving signal based on the digital outphased IF signal; a second stage comprising an inverter circuit to couple to the input of the GaN PA circuit and drive the GaN PA circuit based on the driving signal; and wherein the driving signal provides a 0 to V DD s wing s of the first cascode transistor arrangement. New
The transmitter system of claim 26, wherein driving circuit are implemented on the same chip. uffi c ient to switch on the lower switching device the two-stage driver circuit and the GaN PA New
Layer stacks claimed or described, ordered top of device to substrate.
GaN PA circuit with Modified CMCD configuration and first cascode transistor arrangement
GaN high electron mobility transistor (HEMT) device
GaN PA circuit with inverse CMCD configuration (first and second cascode arrangements)
Materials described outside the worked examples.
Gallium Nitride
GaN
complementary metal-oxide semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak drain efficiency at 1 GHz, 10 W output | 80–85 | GaN |
peak drain efficiency at 1 GHz, 10 W output (abstract/description) | ≥ 85 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,455,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example Doherty amplifier architecture including a main power amplifier (PA) and auxiliary PA. [0006]
FIG. 2 shows a radio frequency (RF) PA architecture using a polar modulation technique. [0007]
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
FIG. 4 shows an example approach for performing out-phasing of an RF signal. [0009]
FIG. 5 shows an example RF transmitter architecture in accordance with embodiments of the present disclosure. [0010]
FIG. 6B shows an example timing diagram and digital logic for performing MUX-based digital upconverting of outphased IF signals, in accordance with an …
FIG. 7 shows a graph that depicts the output spectrum of a simulated 802.1 1 a signal relative to a spectral mask after performing a MUX-based digital …
FIG. 8A showns an example system diagram of an output stage and an antenna driving stage suitable for use in the RF transmitter architecture of
FIG. 9B is a timing diagram showing drain voltage relative to drain currrent over time (t) during operation of the amplifier circuit of
FIG. 10 shows a schematic view of an example inverse Class-D amplifier circuit, in accordance with an embodiment of the present disclosure. [0019]
FIG. 11 illustrates a plurality of inverter circuits suitable for driving the amplifier circuit of
FIG. 12 shows a schematic view of the example inverse Class-D switch mode amplifier circuit of
FIG. 13 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 14 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The transmitter system of claim 1, wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.7.svg 0.15 3.7 Black and white Title: MULTISTANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) Original
The transmitter system of claim 1, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. Original
The transmitter system of claim 1, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Original
The transmitter system of claim 1, wherein the upper switching device and/or the lower switching device comprise high-voltage GaN high electron mobility transistor (HEMT) devices. Original
The transmitter system of claim 1, further comprising the antenna driving circuit, and wherein the antenna driving circuit is implemented on a different chip than the GaN PA circuit. Original
8-9. Canceled
Canceled
The transmitter system of claim 1, further comprising a digital upconvert stage, the digital upconvert stage comprising: an intermediate frequency (IF) processor for receiving a first signal (I (t)) representing an in-phase component of an output waveform and a second signal (Q(t)) representing the quadrature component of the output waveform, and outputting a first and second set of outphased IF signals; and digital upconvert circuitry to receive the first and second set of outphased IF signals and digitally upconvert the first and second set of outphased IF signals to provide the RF signal for driving the GaN PA circuit. Original
The transmitter system of claim 10, wherein the digital upconvert stage is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC). Original
The transmitter system of claim 10, wherein the digital upconvert stage and the output stage are electrically coupled via a 50 ohm terminated transmission line. Original
A method for digitally upconverting an intermediate frequency (IF) signal, the method comprising: receiving a first outphased signal (V I) and a second outphased signal (V Q), multiplying the first outphased signal (V I) with a first multi-level digital clock signal (L O 1 (t)) to provide a first digitally upconverted signal at a first carrier frequency; and multiplying the second outphased signal (V Q) with a second multi-level digital clock signal (LO I (q)) to provide a second digitally upconverted signal at the first carrier frequency) wherein the first and second multi-level digital clock signals each comprise signal levels of-1V, O V, and +1V. Currently amended
The method of claim 13, further comprising summing the first and second outphased signals to derive an RF signal to provide to a PA stage based on the following equation: SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.8.svg 0.18 2.43 Black and white Original
Canceled
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) when operating at a frequency of substantially 1 Gigahertz (GHz) and an output power substantially equal to 10 Watts (W). Currently amended
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Currently amended
The transmitter system [[device]]of claim 21, [[16,]]wherein the upconvert circuit is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) and is electrically coupled to the output stage via a 50 ohm terminated transmission line. Currently amended
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the upper switching device of the first cascode transistor SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.9.svg 0.16 2.9 Black and white Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) New
The transmitter system of claim 21, further comprising an upconvert circuit having a plurality of stages to digitally upconvert outphased IF signals and provide an upconverted outphased digital RF signal; and wherein the output stage further comprises: an amplification circuit to receive the outphased digital RF signal and generate a driving signal based on outphased digital RF signal; and a driving circuit comprising an inverter circuit to drive said GaN PA circuit based on the driving signal. New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration. New
The transmitter system of claim 23, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. New
The transmitter system of claim 23, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W). New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; wherein the output stage further comprises a two-stage driver circuit, the two-stage driver circuit comprising: a first stage to receive a digital outphased intermediate frequency (IF) signal and generate a driving signal based on the digital outphased IF signal; a second stage comprising an inverter circuit to couple to the input of the GaN PA circuit and drive the GaN PA circuit based on the driving signal; and wherein the driving signal provides a 0 to V DD s wing s of the first cascode transistor arrangement. New
The transmitter system of claim 26, wherein driving circuit are implemented on the same chip. uffi c ient to switch on the lower switching device the two-stage driver circuit and the GaN PA New
Layer stacks claimed or described, ordered top of device to substrate.
GaN PA circuit with Modified CMCD configuration and first cascode transistor arrangement
GaN high electron mobility transistor (HEMT) device
GaN PA circuit with inverse CMCD configuration (first and second cascode arrangements)
Materials described outside the worked examples.
Gallium Nitride
GaN
complementary metal-oxide semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak drain efficiency at 1 GHz, 10 W output | 80–85 | GaN |
peak drain efficiency at 1 GHz, 10 W output (abstract/description) | ≥ 85 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,455,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example Doherty amplifier architecture including a main power amplifier (PA) and auxiliary PA. [0006]
FIG. 2 shows a radio frequency (RF) PA architecture using a polar modulation technique. [0007]
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
FIG. 4 shows an example approach for performing out-phasing of an RF signal. [0009]
FIG. 5 shows an example RF transmitter architecture in accordance with embodiments of the present disclosure. [0010]
FIG. 6B shows an example timing diagram and digital logic for performing MUX-based digital upconverting of outphased IF signals, in accordance with an …
FIG. 7 shows a graph that depicts the output spectrum of a simulated 802.1 1 a signal relative to a spectral mask after performing a MUX-based digital …
FIG. 8A showns an example system diagram of an output stage and an antenna driving stage suitable for use in the RF transmitter architecture of
FIG. 9B is a timing diagram showing drain voltage relative to drain currrent over time (t) during operation of the amplifier circuit of
FIG. 10 shows a schematic view of an example inverse Class-D amplifier circuit, in accordance with an embodiment of the present disclosure. [0019]
FIG. 11 illustrates a plurality of inverter circuits suitable for driving the amplifier circuit of
FIG. 12 shows a schematic view of the example inverse Class-D switch mode amplifier circuit of
FIG. 13 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 14 is a graph that illustrates drain efficiency and peak added efficiency for the amplifier circuit of
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The transmitter system of claim 1, wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.7.svg 0.15 3.7 Black and white Title: MULTISTANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) Original
The transmitter system of claim 1, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. Original
The transmitter system of claim 1, wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Original
The transmitter system of claim 1, wherein the upper switching device and/or the lower switching device comprise high-voltage GaN high electron mobility transistor (HEMT) devices. Original
The transmitter system of claim 1, further comprising the antenna driving circuit, and wherein the antenna driving circuit is implemented on a different chip than the GaN PA circuit. Original
8-9. Canceled
Canceled
The transmitter system of claim 1, further comprising a digital upconvert stage, the digital upconvert stage comprising: an intermediate frequency (IF) processor for receiving a first signal (I (t)) representing an in-phase component of an output waveform and a second signal (Q(t)) representing the quadrature component of the output waveform, and outputting a first and second set of outphased IF signals; and digital upconvert circuitry to receive the first and second set of outphased IF signals and digitally upconvert the first and second set of outphased IF signals to provide the RF signal for driving the GaN PA circuit. Original
The transmitter system of claim 10, wherein the digital upconvert stage is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC). Original
The transmitter system of claim 10, wherein the digital upconvert stage and the output stage are electrically coupled via a 50 ohm terminated transmission line. Original
A method for digitally upconverting an intermediate frequency (IF) signal, the method comprising: receiving a first outphased signal (V I) and a second outphased signal (V Q), multiplying the first outphased signal (V I) with a first multi-level digital clock signal (L O 1 (t)) to provide a first digitally upconverted signal at a first carrier frequency; and multiplying the second outphased signal (V Q) with a second multi-level digital clock signal (LO I (q)) to provide a second digitally upconverted signal at the first carrier frequency) wherein the first and second multi-level digital clock signals each comprise signal levels of-1V, O V, and +1V. Currently amended
The method of claim 13, further comprising summing the first and second outphased signals to derive an RF signal to provide to a PA stage based on the following equation: SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.8.svg 0.18 2.43 Black and white Original
Canceled
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) when operating at a frequency of substantially 1 Gigahertz (GHz) and an output power substantially equal to 10 Watts (W). Currently amended
Canceled
The transmitter system [[device]]of claim 21, [[16,]]wherein the upper switching device and the lower switching device of the first cascode transistor arrangement comprise GaN field-effect transistor devices (FETs). Currently amended
The transmitter system [[device]]of claim 21, [[16,]]wherein the upconvert circuit is implemented as a complementary metal-oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) and is electrically coupled to the output stage via a 50 ohm terminated transmission line. Currently amended
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the upper switching device of the first cascode transistor SVG 15974809.05-17-2019.JVSDHM₆₇RXEAPX3.CLM.9.svg 0.16 2.9 Black and white Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) New
The transmitter system of claim 21, further comprising an upconvert circuit having a plurality of stages to digitally upconvert outphased IF signals and provide an upconverted outphased digital RF signal; and wherein the output stage further comprises: an amplification circuit to receive the outphased digital RF signal and generate a driving signal based on outphased digital RF signal; and a driving circuit comprising an inverter circuit to drive said GaN PA circuit based on the driving signal. New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; and wherein the GaN PA circuit includes a second cascode transistor arrangement, the first and second cascode switching arrangements forming an inverse CMCD configuration. New
The transmitter system of claim 23, wherein the upper switching device of the first cascode transistor arrangement is 1.22 ± 0.2 millimeters wide. New
The transmitter system of claim 23, wherein the GaN PA circuit operates at a peak drain efficiency between 80% to 85% when operating at a frequency of Title: MULTI-STANDARD TRANSMITTER ARCHITECTURE WITH DIGITAL UPCONVERT STAGE AND GALLIUM NITRIDE (GAN) substantially 1 Gigahertz (GHz) and has an output power substantially equal to 10 Watts (W). New
A transmitter system comprising: an output stage comprising: a Gallium Nitride (GaN) power amplifier (PA) circuit having a Modified Current Mode Class-D (CMCD) configuration, the GaN PA circuit including: a lower switching device electrically coupled to an input to receive an input RF signal; an upper switching device to switchably couple the first switching device to a power supply to drive an antenna circuit based on the input RF signal; and wherein the lower and upper switching devices form a first transistor cascode arrangement; wherein the output stage further comprises a two-stage driver circuit, the two-stage driver circuit comprising: a first stage to receive a digital outphased intermediate frequency (IF) signal and generate a driving signal based on the digital outphased IF signal; a second stage comprising an inverter circuit to couple to the input of the GaN PA circuit and drive the GaN PA circuit based on the driving signal; and wherein the driving signal provides a 0 to V DD s wing s of the first cascode transistor arrangement. New
The transmitter system of claim 26, wherein driving circuit are implemented on the same chip. uffi c ient to switch on the lower switching device the two-stage driver circuit and the GaN PA New
Layer stacks claimed or described, ordered top of device to substrate.
GaN PA circuit with Modified CMCD configuration and first cascode transistor arrangement
GaN high electron mobility transistor (HEMT) device
GaN PA circuit with inverse CMCD configuration (first and second cascode arrangements)
Materials described outside the worked examples.
Gallium Nitride
GaN
complementary metal-oxide semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows a graph illustrating the amplitude and phase signals for an Enhanced Data rates for GSM Evolution (EDGE) system relative to a target spectral …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak drain efficiency at 1 GHz, 10 W output | 80–85 | GaN |
peak drain efficiency at 1 GHz, 10 W output (abstract/description) | ≥ 85 |
Related documents with shared materials, methods, properties, or citations.
GaN PA circuit with two-stage driver circuit
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
GaN PA circuit with two-stage driver circuit
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
GaN PA circuit with two-stage driver circuit
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of
GaN PA circuit with two-stage driver circuit
FIG. 15 is a graph illustrating the output spectrum of the amplifier circuit of