DATA STORAGE DEVICE CONFIGURED FOR USE WITH A GENERATIVE-ADVERSARIAL-NETWORK (GAN)

Daniel Joseph Linnen; William Bernard Boyle; Ariel Navon; Shay Benisty; Alexander Bazarsky

Patent

Atlas literature

Patent

US 12,399,814 B2

DATA STORAGE DEVICE CONFIGURED FOR USE WITH A GENERATIVE-ADVERSARIAL-NETWORK (GAN)

Daniel Joseph Linnen, William Bernard Boyle, Ariel Navon, Shay Benisty et al.

Sandisk Technologies, Inc., Milpitas, CA (US)·Aug. 26, 2025·US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a schematic block diagram of a data storage device in the form of an exemplary solid state device (SSD), or other data storage device (DSD), having a …

FIG. 2

FIG. 2 illustrates exemplary components of a DSD that has a main memory partition and a GAN memory partition and various components for GAN-based processing …

FIG. 3

FIG. 3 illustrates an exemplary method for a write path for storing data in a GAN memory partition, in accordance with aspects of the disclosure.

FIG. 4

FIG. 4 illustrates an exemplary method for a read path for decoding data read from an NVM using a GAN, in accor- dance with aspects of the disclosure.

FIG. 5

FIG. 5 illustrates an exemplary alternate method for a read path for decoding data read from an NVM using a GAN, in accordance with aspects of the disclosure.

FIG. 6

FIG. 6 illustrates additional features of an exemplary method for a write path for storing data to an NVM in which some data is stored in a main memory …

FIG. 7

FIG. 7 illustrates features of an exemplary method for a read path for reading data from an NVM with GAN-based pre-processing to generate soft information …

FIG. 8

FIG. 8 illustrates features of an exemplary method for dissimilarity matrix processing, in accordance with aspects of the disclosure.

FIG. 9

FIG. 9 illustrates features of an exemplary method for using GAN-based soft bit conﬁdence information, in accor- dance with aspects of the disclosure.

FIG. 10

performance graph

FIG. 10 is a graph illustrating voltage read levels used to deﬁne and identify valley bits for use with GAN processing, in accordance with aspects of the …

FIG. 11

FIG. 11 illustrates a ﬁrst exemplary method for valley-bit based processing with GANs, in accordance with aspects of the disclosure.

FIG. 12

FIG. 12 illustrates a second exemplary method for valley- bit based processing with GANs, in accordance with aspects of the disclosure.

FIG. 13

performance graph

FIG. 13 is a graph illustrating additional voltage read levels that may be used to deﬁne and identify valley bits for use with GAN processing, in accordance …

FIG. 14

FIG. 14 illustrates features of an exemplary method in which high conﬁdence data is “unﬂipped” if changed by a GAN, in accordance with aspects of the …

FIG. 15

FIG. 15 illustrates features of an exemplary method for GAN outcome aggregation. in accordance with aspects of 5 the disclosure.

FIG. 16

FIG. 16 illustrates additional features of an exemplary method for GAN outcome aggregation, in accordance with aspects of the disclosure.

FIG. 17

FIG. 17 is a schematic block diagram conﬁguration for an 10 exemplary DSD having an NVM and a controller conﬁgured to decode data using a decoding procedure …

FIG. 18

FIG. 18 illustrates an exemplary method for decoding 15 data using a decoding procedure that includes a GAN procedure, in accordance with aspects of the …

FIG. 19

FIG. 19 is a schematic block diagram conﬁguration for an exemplary DSD having an NVM and a controller conﬁgured to decode data by applying an LDPC procedure to …

FIG. 20

FIG. 20 illustrates an exemplary method for decoding data by applying an LDPC procedure to the data along with 25 GAN-based soft bit information generated by a …

FIG. 21

FIG. 21 is a schematic block diagram conﬁguration for an exemplary DSD having an NVM and a controller conﬁgured to process data using a GAN procedure that …

FIG. 22

FIG. 22 illustrates an exemplary method for processing data using a GAN procedure conﬁgured to use the conﬁ- dence information to reconstruct the data, in …

FIG. 23

FIG. 23 is a schematic block diagram conﬁguration for an exemplary apparatus such as a DSD having GAN-based features.

FIG. 1100

FIG. 1100 is done. On the other hand, if the Count of Valley Bits 2 is not 25 below the threshold, processing proceeds to block 1132, where the processor …

FIG. 1200

FIG. 1200 is done. On the other hand. if the Count of Valley Bits 2 is not below the threshold in block 1228, processing proceeds to block 1232, where the …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 21 dependent

1
Independentdata storage device with GAN-based image reconstruction
A data storage device, comprising: a non-volatile memory (NVM); a data storage controller coupled to the NVM, the data storage controller comprising one or more processors conﬁgured, individually or in combination, to: read pixels representing an image from the NVM, generate conﬁdence information representative of a conﬁdence in the reliability of the reading of the pixels from the NVM, the conﬁdence information comprising a set of bits that quantify the reliability within a range of reliability values that comprises at least three different reliability values; modify the pixels read from the NVM to each include the set of bits that represent the conﬁdence informa-tion; and reconstruct the image with the modiﬁed pixels by processing the data using a generative-adversarial-network (GAN) procedure that is conﬁgured to reconstruct images comprising pixels that include the set of bits that represent the conﬁdence informa-tion.
1. 2
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the one or more processors are further conﬁgured to generate the conﬁdence information by being further conﬁgured to gen-erate soft bits.
2. 4
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the one or more processors are further conﬁgured to generate the conﬁdence information by being further conﬁgured to: perform a preliminary reconstruction of the image using a plurality of different GAN procedures without using any conﬁdence information; and determine whether the plurality of different GAN proce-dures yielded the same reconstructed image as one another.
3. 8
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the one or more processors are further conﬁgured to generate the conﬁdence information by being further conﬁgured to: perform ﬁrst and second senses of bits of the data at ﬁrst and second different read voltages to obtain ﬁrst and second reads of the data; identify a set of valley bits within the ﬁrst and second reads of the data; and generate the conﬁdence information from the set of valley bits.
4. 9
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the one or more processors are further conﬁgured to adjust read volt-ages based on the conﬁdence information.
5. 10
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the data storage controller further comprises a plurality of GAN processors conﬁgured to perform separate GAN procedures to reconstruct the image with the pixels that include the conﬁdence information and to combine results of the sepa-rate GAN procedures.
6. 16
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the one or more processors are further conﬁgured to generate the conﬁdence information using one or more of a rules-based procedure or an inference-based procedure.
7. 17
  Dependent← claim 1data storage device with GAN-based image reconstruction
  The data storage device of claim 1, wherein the at least three different reliability values comprise a minimum reli-ability value, a maximum reliability value, and at least one intermediate reliability value.
18
Independent
A method, comprising: reading pixels representing an image from a non-volatile memory (NVM) of a data storage device; generating conﬁdence information representative of a conﬁdence in the reliability of the reading of the pixels from the NVM, the conﬁdence information comprising a set of bits that quantify the reliability within a range of reliability values that comprises at least three dif-ferent reliability values; modifying the pixels read from the NVM to each include the set of bits that represent the conﬁdence information; and reconstructing the image with the modiﬁed pixels by processing the data using a generative-adversarial-net-work (GAN) procedure that is conﬁgured to reconstruct images comprising pixels that include the set of bits that represent the conﬁdence information.
1. 19
  Dependent← claim 18
  The method of claim 18, further comprising generat-ing the conﬁdence information by: performing a preliminary reconstruction of the image using a plurality of different GAN procedures without using any conﬁdence information; and determining whether the plurality of different GAN pro-cedures yielded the same reconstructed image as one another.
2. 20
  Dependent← claim 18
  The method of claim 18, further comprising generat-ing the conﬁdence information by: performing ﬁrst and second senses of bits of the data at ﬁrst and second different read voltages to obtain ﬁrst and second reads of the data; identifying a ﬁrst set of valley bits within the ﬁrst and second reads of the data; and generating the conﬁdence information from the set of valley bits.
3. 21
  Dependent← claim 18
  The method of claim 18, wherein the at least three different reliability values comprise a minimum reliability value, a maximum reliability value, and at least one intermediate reliability value.
22
Independent
An apparatus for use in a data storage device com-prising a data storage controller comprising one or more processors, the apparatus comprising: means for reading pixels representing an image from a non-volatile memory (NVM) of the data storage device; means for generating conﬁdence information representative of a conﬁdence in the reliability of the reading of the pixels from the NVM, the conﬁdence information comprising a set of bits that quantify the reliability within a range of reliability values that com-39 prises at least three different reliability values; means for modifying the pixels read from the NVM to each include the set of bits that represent the conﬁdence information; and means for reconstructing the image with the modiﬁed pixels by processing the data using a generative-adversarial-net-work (GAN) procedure that is conﬁgured to reconstruct images comprising pixels that include the set of bits that represent the conﬁdence information.
1. 23
  Dependent← claim 22
  The apparatus of claim 22, wherein the at least three different reliability values comprise a minimum reliability value, a maximum reliability value, and at least one intermediate reliability value.
2. 24
  Dependent← claim 22
  The apparatus of claim 22, further comprising: means for adjusting read voltages based on the conﬁdence infor-mation. ∗ ∗ ∗ ∗ ∗

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

data storage device with GAN-based image reconstruction

data storage controller with GAN processor(s)data storage controller with GAN processor(s)

non-volatile memory (NVM)non-volatile memory (NVM)

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

device performance measurement

Device Performance Measurement

FIG. 10 is a graph illustrating voltage read levels used to deﬁne and identify valley bits for use with GAN processing, in accordance with aspects of the …

Figure references

FIG. 10

device performance measurement

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 29

US 6,963,369 B16,963,369 B1 * 11/2005 Olding................. H04N 25/616examiner
US 10,554,227 B210,554,227 B2 2/2020 Sharon et al.
CN 111986079 ACN 111986079 A 11/2020
KR 20220004476 AKR 20220004476 A 1/2022
WO 2020256787 A1WO 2020256787 A1 12/2020
US 11,010,233 B111,010,233 B1 5/2021 Golden et al.

Why these are connected

Related documents with shared materials, methods, properties, or citations.

DATA STORAGE DEVICE CONFIGURED FOR USE WITH A GENERATIVE-ADVERSARIAL-NETWORK (GAN) | Matter42 Literature

Cited non-patent literature · 14

Kyle Dunphy, DataAugmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Information, Aug. 2022, Sensors, vol. 22, Issue 16, pp. 3-5, 13-15, 19 (Year: 2022).
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM. Chen, Fan et al., “Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM”, Spe- cial Session 3: Recent Advances in Near and In-Memory Comput- ing Circuit and Architecture for Artiﬁcial Intelligence and Machine Learning; May 9-11, 2019; https://par.nsf.gov/servlets/purl/10112454; 6 pages.
IMAGING: In-Memory AlGorithms for Image processiNG. Ali, Ameer Haj et al., “IMAGING: In-Memory AlGorithms for Image processiNG”, Circuits and Systems I: Regular Papers; IEEE Transactions; Jun. 2018; https://www.researchgate.net/publication/326027425_IMAGING_In-Memory_AlGorithms_for_Image_ processiNG; 15 pages.
Generative Adversarial Networks with Decoder-Encoder Output Noise. Zhong, Guoqiang et al., “Generative Adversarial Networks with Decoder-Encoder Output Noise”, Computer Science: Computer Vision and Pattern Recognition; Cornell University; Jul. 11, 2018; https://arxiv.org/pdf/1807.03923.pdf; 12 pages.
SRAF Placement with Generative Adversarial Network. Ciou, Weilun et al., “SRAF Placement with Generative Adversarial Network”, Proceedings vol. 11613; Optical Microlithography XXXIV (1161305); SPIE Advanced Lithography; Feb. 22, 2021; https://doi. org/10.1117/12.2581334; 2 pages.10.1117/12.2581334
A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction. Wang, Yufei et al., “A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction”, Journal of Intelligent & Fuzzy Systems; vol. 43, No., 4; Aug. 10, 2022; https://content.ospress.com/articles/journal-of-intelligent-and- fuzzy-systems/ifs220590; 2 pages.
Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks. Huang, Wei et al., “Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks”, Neuroscience Bulletin 37; Nov. 22, 2020; https://link.springer.com/article/10.1007/s12264-020- 00613-4; 21 pages.10.1007/s12264-020
Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network. Ledig, Christian et al., “Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network”, Computer Science: Computer Vision and Pattern Recognition; Cornell Uni- versity; Sep. 15, 2016; https://arxiv.org/abs/1609.04802; 19 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/012754, dated May 27, 2024, 11 pages.
Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion. Dunphy, Kyle et al., “Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion”, MDPI; Aug. 18, 2022; https://doi.org/10.3390/s22166193; 30 pages.10.3390/s22166193
Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation. Hwang, Minyoung et al., “Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation”, IEEE Access; vol. 10; Nov. 7, 2022; https://ieeexplore.ieee.org/document/9940942; 17 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/013535, dated Jun. 3, 2024, 8 pages.
Error Generation for 3D NAND Flash Memory. Liu, Weihua et al., “Error Generation for 3D NAND Flash Memory”, 2022 Design, Automation & Test in Europe Conference & Exhibi- tion; Mar. 14-23, 2022; https://ieeexplore.ieee.org/document/9774514; 5 pages.
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. Zhang, Meng et al., “BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory”, 2020 Design, Automation & Test in Europe Conference & Exhibition; Mar. 9-13, 2020; https://ieeexplore.IEEE.org/document/9116324; 5 pages.
Generative Adversarial Nets. Goodfellow, Ian J. et al., “Generative Adversarial Nets”, Cornell University; Statistics: Machine Learning; Jun. 10, 2014; https://doi. org/10.48550/arXiv.1406.2661; 9 pages.10.48550/arXiv.1406.2661
Generative Adversarial Networks for Unsupervised Fault Detection. Spyridon, Plakias et al., “Generative Adversarial Networks for Unsupervised Fault Detection”, 2018 European Control Conference (ECC); Limassol, Cyprus; Jun. 12-15, 2018, https://ieeexplore.IEEE. org/document/8550560; 6 Pages.

Cited non-patent literature · 14

Kyle Dunphy, DataAugmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Information, Aug. 2022, Sensors, vol. 22, Issue 16, pp. 3-5, 13-15, 19 (Year: 2022).
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM. Chen, Fan et al., “Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM”, Spe- cial Session 3: Recent Advances in Near and In-Memory Comput- ing Circuit and Architecture for Artiﬁcial Intelligence and Machine Learning; May 9-11, 2019; https://par.nsf.gov/servlets/purl/10112454; 6 pages.
IMAGING: In-Memory AlGorithms for Image processiNG. Ali, Ameer Haj et al., “IMAGING: In-Memory AlGorithms for Image processiNG”, Circuits and Systems I: Regular Papers; IEEE Transactions; Jun. 2018; https://www.researchgate.net/publication/326027425_IMAGING_In-Memory_AlGorithms_for_Image_ processiNG; 15 pages.
Generative Adversarial Networks with Decoder-Encoder Output Noise. Zhong, Guoqiang et al., “Generative Adversarial Networks with Decoder-Encoder Output Noise”, Computer Science: Computer Vision and Pattern Recognition; Cornell University; Jul. 11, 2018; https://arxiv.org/pdf/1807.03923.pdf; 12 pages.
SRAF Placement with Generative Adversarial Network. Ciou, Weilun et al., “SRAF Placement with Generative Adversarial Network”, Proceedings vol. 11613; Optical Microlithography XXXIV (1161305); SPIE Advanced Lithography; Feb. 22, 2021; https://doi. org/10.1117/12.2581334; 2 pages.10.1117/12.2581334
A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction. Wang, Yufei et al., “A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction”, Journal of Intelligent & Fuzzy Systems; vol. 43, No., 4; Aug. 10, 2022; https://content.ospress.com/articles/journal-of-intelligent-and- fuzzy-systems/ifs220590; 2 pages.
Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks. Huang, Wei et al., “Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks”, Neuroscience Bulletin 37; Nov. 22, 2020; https://link.springer.com/article/10.1007/s12264-020- 00613-4; 21 pages.10.1007/s12264-020
Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network. Ledig, Christian et al., “Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network”, Computer Science: Computer Vision and Pattern Recognition; Cornell Uni- versity; Sep. 15, 2016; https://arxiv.org/abs/1609.04802; 19 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/012754, dated May 27, 2024, 11 pages.
Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion. Dunphy, Kyle et al., “Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion”, MDPI; Aug. 18, 2022; https://doi.org/10.3390/s22166193; 30 pages.10.3390/s22166193
Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation. Hwang, Minyoung et al., “Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation”, IEEE Access; vol. 10; Nov. 7, 2022; https://ieeexplore.ieee.org/document/9940942; 17 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/013535, dated Jun. 3, 2024, 8 pages.
Error Generation for 3D NAND Flash Memory. Liu, Weihua et al., “Error Generation for 3D NAND Flash Memory”, 2022 Design, Automation & Test in Europe Conference & Exhibi- tion; Mar. 14-23, 2022; https://ieeexplore.ieee.org/document/9774514; 5 pages.
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. Zhang, Meng et al., “BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory”, 2020 Design, Automation & Test in Europe Conference & Exhibition; Mar. 9-13, 2020; https://ieeexplore.IEEE.org/document/9116324; 5 pages.
Generative Adversarial Nets. Goodfellow, Ian J. et al., “Generative Adversarial Nets”, Cornell University; Statistics: Machine Learning; Jun. 10, 2014; https://doi. org/10.48550/arXiv.1406.2661; 9 pages.10.48550/arXiv.1406.2661
Generative Adversarial Networks for Unsupervised Fault Detection. Spyridon, Plakias et al., “Generative Adversarial Networks for Unsupervised Fault Detection”, 2018 European Control Conference (ECC); Limassol, Cyprus; Jun. 12-15, 2018, https://ieeexplore.IEEE. org/document/8550560; 6 Pages.

Cited non-patent literature · 14

Kyle Dunphy, DataAugmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Information, Aug. 2022, Sensors, vol. 22, Issue 16, pp. 3-5, 13-15, 19 (Year: 2022).
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM. Chen, Fan et al., “Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM”, Spe- cial Session 3: Recent Advances in Near and In-Memory Comput- ing Circuit and Architecture for Artiﬁcial Intelligence and Machine Learning; May 9-11, 2019; https://par.nsf.gov/servlets/purl/10112454; 6 pages.
IMAGING: In-Memory AlGorithms for Image processiNG. Ali, Ameer Haj et al., “IMAGING: In-Memory AlGorithms for Image processiNG”, Circuits and Systems I: Regular Papers; IEEE Transactions; Jun. 2018; https://www.researchgate.net/publication/326027425_IMAGING_In-Memory_AlGorithms_for_Image_ processiNG; 15 pages.
Generative Adversarial Networks with Decoder-Encoder Output Noise. Zhong, Guoqiang et al., “Generative Adversarial Networks with Decoder-Encoder Output Noise”, Computer Science: Computer Vision and Pattern Recognition; Cornell University; Jul. 11, 2018; https://arxiv.org/pdf/1807.03923.pdf; 12 pages.
SRAF Placement with Generative Adversarial Network. Ciou, Weilun et al., “SRAF Placement with Generative Adversarial Network”, Proceedings vol. 11613; Optical Microlithography XXXIV (1161305); SPIE Advanced Lithography; Feb. 22, 2021; https://doi. org/10.1117/12.2581334; 2 pages.10.1117/12.2581334
A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction. Wang, Yufei et al., “A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction”, Journal of Intelligent & Fuzzy Systems; vol. 43, No., 4; Aug. 10, 2022; https://content.ospress.com/articles/journal-of-intelligent-and- fuzzy-systems/ifs220590; 2 pages.
Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks. Huang, Wei et al., “Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks”, Neuroscience Bulletin 37; Nov. 22, 2020; https://link.springer.com/article/10.1007/s12264-020- 00613-4; 21 pages.10.1007/s12264-020
Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network. Ledig, Christian et al., “Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network”, Computer Science: Computer Vision and Pattern Recognition; Cornell Uni- versity; Sep. 15, 2016; https://arxiv.org/abs/1609.04802; 19 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/012754, dated May 27, 2024, 11 pages.
Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion. Dunphy, Kyle et al., “Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion”, MDPI; Aug. 18, 2022; https://doi.org/10.3390/s22166193; 30 pages.10.3390/s22166193
Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation. Hwang, Minyoung et al., “Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation”, IEEE Access; vol. 10; Nov. 7, 2022; https://ieeexplore.ieee.org/document/9940942; 17 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/013535, dated Jun. 3, 2024, 8 pages.
Error Generation for 3D NAND Flash Memory. Liu, Weihua et al., “Error Generation for 3D NAND Flash Memory”, 2022 Design, Automation & Test in Europe Conference & Exhibi- tion; Mar. 14-23, 2022; https://ieeexplore.ieee.org/document/9774514; 5 pages.
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. Zhang, Meng et al., “BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory”, 2020 Design, Automation & Test in Europe Conference & Exhibition; Mar. 9-13, 2020; https://ieeexplore.IEEE.org/document/9116324; 5 pages.
Generative Adversarial Nets. Goodfellow, Ian J. et al., “Generative Adversarial Nets”, Cornell University; Statistics: Machine Learning; Jun. 10, 2014; https://doi. org/10.48550/arXiv.1406.2661; 9 pages.10.48550/arXiv.1406.2661
Generative Adversarial Networks for Unsupervised Fault Detection. Spyridon, Plakias et al., “Generative Adversarial Networks for Unsupervised Fault Detection”, 2018 European Control Conference (ECC); Limassol, Cyprus; Jun. 12-15, 2018, https://ieeexplore.IEEE. org/document/8550560; 6 Pages.

Cited non-patent literature · 14

Kyle Dunphy, DataAugmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Information, Aug. 2022, Sensors, vol. 22, Issue 16, pp. 3-5, 13-15, 19 (Year: 2022).
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM. Chen, Fan et al., “Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM”, Spe- cial Session 3: Recent Advances in Near and In-Memory Comput- ing Circuit and Architecture for Artiﬁcial Intelligence and Machine Learning; May 9-11, 2019; https://par.nsf.gov/servlets/purl/10112454; 6 pages.
IMAGING: In-Memory AlGorithms for Image processiNG. Ali, Ameer Haj et al., “IMAGING: In-Memory AlGorithms for Image processiNG”, Circuits and Systems I: Regular Papers; IEEE Transactions; Jun. 2018; https://www.researchgate.net/publication/326027425_IMAGING_In-Memory_AlGorithms_for_Image_ processiNG; 15 pages.
Generative Adversarial Networks with Decoder-Encoder Output Noise. Zhong, Guoqiang et al., “Generative Adversarial Networks with Decoder-Encoder Output Noise”, Computer Science: Computer Vision and Pattern Recognition; Cornell University; Jul. 11, 2018; https://arxiv.org/pdf/1807.03923.pdf; 12 pages.
SRAF Placement with Generative Adversarial Network. Ciou, Weilun et al., “SRAF Placement with Generative Adversarial Network”, Proceedings vol. 11613; Optical Microlithography XXXIV (1161305); SPIE Advanced Lithography; Feb. 22, 2021; https://doi. org/10.1117/12.2581334; 2 pages.10.1117/12.2581334
A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction. Wang, Yufei et al., “A Novel SSD Fault Detection Method using GRU-based Sparse Auto-Encoder for Dimensionality Reduction”, Journal of Intelligent & Fuzzy Systems; vol. 43, No., 4; Aug. 10, 2022; https://content.ospress.com/articles/journal-of-intelligent-and- fuzzy-systems/ifs220590; 2 pages.
Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks. Huang, Wei et al., “Deep Natural Image Reconstruction from Human Brain Activity Based on Conditional Progressively Growing Generative Adversarial Networks”, Neuroscience Bulletin 37; Nov. 22, 2020; https://link.springer.com/article/10.1007/s12264-020- 00613-4; 21 pages.10.1007/s12264-020
Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network. Ledig, Christian et al., “Photo-Realistic Single Image Super- Resolution Using a Generative Adversarial Network”, Computer Science: Computer Vision and Pattern Recognition; Cornell Uni- versity; Sep. 15, 2016; https://arxiv.org/abs/1609.04802; 19 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/012754, dated May 27, 2024, 11 pages.
Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion. Dunphy, Kyle et al., “Data Augmentation for Deep-Learning-Based Multiclass Structural Damage Detection Using Limited Informa- tion”, MDPI; Aug. 18, 2022; https://doi.org/10.3390/s22166193; 30 pages.10.3390/s22166193
Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation. Hwang, Minyoung et al., “Dynamic Error Recovery Flow Predic- tion Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation”, IEEE Access; vol. 10; Nov. 7, 2022; https://ieeexplore.ieee.org/document/9940942; 17 pages. International Search Report and Written Opinion for International Application No. PCT/US2024/013535, dated Jun. 3, 2024, 8 pages.
Error Generation for 3D NAND Flash Memory. Liu, Weihua et al., “Error Generation for 3D NAND Flash Memory”, 2022 Design, Automation & Test in Europe Conference & Exhibi- tion; Mar. 14-23, 2022; https://ieeexplore.ieee.org/document/9774514; 5 pages.
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. Zhang, Meng et al., “BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory”, 2020 Design, Automation & Test in Europe Conference & Exhibition; Mar. 9-13, 2020; https://ieeexplore.IEEE.org/document/9116324; 5 pages.
Generative Adversarial Nets. Goodfellow, Ian J. et al., “Generative Adversarial Nets”, Cornell University; Statistics: Machine Learning; Jun. 10, 2014; https://doi. org/10.48550/arXiv.1406.2661; 9 pages.10.48550/arXiv.1406.2661
Generative Adversarial Networks for Unsupervised Fault Detection. Spyridon, Plakias et al., “Generative Adversarial Networks for Unsupervised Fault Detection”, 2018 European Control Conference (ECC); Limassol, Cyprus; Jun. 12-15, 2018, https://ieeexplore.IEEE. org/document/8550560; 6 Pages.