Patent
US 12,142,674 B2GALLIUM NITRIDE HIGH-ELECTRON MOBILITY TRANSISTORS WITH P-TYPE LAYERS AND PROCESS FOR MAKING THE SAME
Saptharishi Sriram
WOLFSPEED, INC., Durham, NC (US)·Nov. 12, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,142,674 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
FIG. 2 shows another cross-sectional view of the transis- tor of
FIG. 3 shows another cross-sectional view of the transis- tor of
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor comprising: a substrate layer; a buffer layer arranged on the substrate layer; a barrier layer arranged on the buffer layer; a drain arranged on the barrier layer; a gate arranged on the barrier layer; a source arranged on the barrier layer; the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to increase discharge efficiency and limit breakdown.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to retard an electric field, to increase electron confinement, and decrease leakage.
The high-electron mobility transistor of claim 1, further comprising: a plurality of unit cells; and the plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The high-electron mobility transistor of claim 1, further comprising: a p-type material contact arranged on and electrically coupled to the p-type material layer; and 30 a nucleation layer arranged on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The high-electron mobility transistor of claim 1, further comprising: 40 a recess in at least the barrier layer; the source comprises a p-type material contact arranged in the recess; and the p-type material contact is arranged on and electrically coupled to the p-type material layer.
The high-electron mobility transistor of claim 1, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The high-electron mobility transistor of claim 1, further comprising: a second buffer layer arranged on the buffer layer on a side of the buffer layer opposite of the substrate layer, wherein the barrier layer is arranged on the second buffer layer on a side opposite of the buffer layer.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 60% to 80% of a B₂ gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
A process of making high-electron mobility transistor comprising: providing a substrate layer; arranging a buffer layer on the substrate layer; arranging a barrier layer arranged on the buffer layer; arranging a source on the barrier layer; arranging a drain on the barrier layer; arranging a gate on the barrier layer; configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an B₂ heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to increase discharge efficiency and limit breakdown.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to retard an electric field, to increase electron confinement, and decrease leakage.
The process of making high-electron mobility tran-sistor of claim 9, further comprising providing a plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: arranging p-type material contact on and electrically coupled to the p-type material layer; and arranging a nucleation layer on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a recess in at least the barrier layer; and forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer; and arranging the p-type material contact on and electrically coupled to the p-type material layer.
The process of making high-electron mobility tran-sistor of claim 9, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: providing a second buffer layer formed on the buffer layer; providing a protective layer formed on the barrier layer; and providing a nucleation layer arranged on the substrate layer, wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the buffer layer to extend at least from the source past the gate and the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the buffer layer.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a nucleation layer on the substrate layer and arranging the buffer layer on the nucleation layer, wherein the substrate layer comprises Silicon Carbide.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a protective layer; arranging a gate in part on the barrier layer and in part on the protective layer; and forming a field plate structure extending a distance away from an edge of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN high-electron mobility transistor (HEMT) with p-type layer
Materials described outside the worked examples.
p-type material layer
buffer layer
barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.4–0.7 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 74
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,142,674 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
FIG. 2 shows another cross-sectional view of the transis- tor of
FIG. 3 shows another cross-sectional view of the transis- tor of
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor comprising: a substrate layer; a buffer layer arranged on the substrate layer; a barrier layer arranged on the buffer layer; a drain arranged on the barrier layer; a gate arranged on the barrier layer; a source arranged on the barrier layer; the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to increase discharge efficiency and limit breakdown.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to retard an electric field, to increase electron confinement, and decrease leakage.
The high-electron mobility transistor of claim 1, further comprising: a plurality of unit cells; and the plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The high-electron mobility transistor of claim 1, further comprising: a p-type material contact arranged on and electrically coupled to the p-type material layer; and 30 a nucleation layer arranged on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The high-electron mobility transistor of claim 1, further comprising: 40 a recess in at least the barrier layer; the source comprises a p-type material contact arranged in the recess; and the p-type material contact is arranged on and electrically coupled to the p-type material layer.
The high-electron mobility transistor of claim 1, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The high-electron mobility transistor of claim 1, further comprising: a second buffer layer arranged on the buffer layer on a side of the buffer layer opposite of the substrate layer, wherein the barrier layer is arranged on the second buffer layer on a side opposite of the buffer layer.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 60% to 80% of a B₂ gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
A process of making high-electron mobility transistor comprising: providing a substrate layer; arranging a buffer layer on the substrate layer; arranging a barrier layer arranged on the buffer layer; arranging a source on the barrier layer; arranging a drain on the barrier layer; arranging a gate on the barrier layer; configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an B₂ heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to increase discharge efficiency and limit breakdown.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to retard an electric field, to increase electron confinement, and decrease leakage.
The process of making high-electron mobility tran-sistor of claim 9, further comprising providing a plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: arranging p-type material contact on and electrically coupled to the p-type material layer; and arranging a nucleation layer on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a recess in at least the barrier layer; and forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer; and arranging the p-type material contact on and electrically coupled to the p-type material layer.
The process of making high-electron mobility tran-sistor of claim 9, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: providing a second buffer layer formed on the buffer layer; providing a protective layer formed on the barrier layer; and providing a nucleation layer arranged on the substrate layer, wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the buffer layer to extend at least from the source past the gate and the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the buffer layer.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a nucleation layer on the substrate layer and arranging the buffer layer on the nucleation layer, wherein the substrate layer comprises Silicon Carbide.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a protective layer; arranging a gate in part on the barrier layer and in part on the protective layer; and forming a field plate structure extending a distance away from an edge of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN high-electron mobility transistor (HEMT) with p-type layer
Materials described outside the worked examples.
p-type material layer
buffer layer
barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.4–0.7 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 74
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,142,674 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
FIG. 2 shows another cross-sectional view of the transis- tor of
FIG. 3 shows another cross-sectional view of the transis- tor of
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor comprising: a substrate layer; a buffer layer arranged on the substrate layer; a barrier layer arranged on the buffer layer; a drain arranged on the barrier layer; a gate arranged on the barrier layer; a source arranged on the barrier layer; the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to increase discharge efficiency and limit breakdown.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to retard an electric field, to increase electron confinement, and decrease leakage.
The high-electron mobility transistor of claim 1, further comprising: a plurality of unit cells; and the plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The high-electron mobility transistor of claim 1, further comprising: a p-type material contact arranged on and electrically coupled to the p-type material layer; and 30 a nucleation layer arranged on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The high-electron mobility transistor of claim 1, further comprising: 40 a recess in at least the barrier layer; the source comprises a p-type material contact arranged in the recess; and the p-type material contact is arranged on and electrically coupled to the p-type material layer.
The high-electron mobility transistor of claim 1, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The high-electron mobility transistor of claim 1, further comprising: a second buffer layer arranged on the buffer layer on a side of the buffer layer opposite of the substrate layer, wherein the barrier layer is arranged on the second buffer layer on a side opposite of the buffer layer.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 60% to 80% of a B₂ gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
A process of making high-electron mobility transistor comprising: providing a substrate layer; arranging a buffer layer on the substrate layer; arranging a barrier layer arranged on the buffer layer; arranging a source on the barrier layer; arranging a drain on the barrier layer; arranging a gate on the barrier layer; configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an B₂ heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to increase discharge efficiency and limit breakdown.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to retard an electric field, to increase electron confinement, and decrease leakage.
The process of making high-electron mobility tran-sistor of claim 9, further comprising providing a plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: arranging p-type material contact on and electrically coupled to the p-type material layer; and arranging a nucleation layer on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a recess in at least the barrier layer; and forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer; and arranging the p-type material contact on and electrically coupled to the p-type material layer.
The process of making high-electron mobility tran-sistor of claim 9, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: providing a second buffer layer formed on the buffer layer; providing a protective layer formed on the barrier layer; and providing a nucleation layer arranged on the substrate layer, wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the buffer layer to extend at least from the source past the gate and the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the buffer layer.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a nucleation layer on the substrate layer and arranging the buffer layer on the nucleation layer, wherein the substrate layer comprises Silicon Carbide.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a protective layer; arranging a gate in part on the barrier layer and in part on the protective layer; and forming a field plate structure extending a distance away from an edge of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN high-electron mobility transistor (HEMT) with p-type layer
Materials described outside the worked examples.
p-type material layer
buffer layer
barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.4–0.7 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 74
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 12,142,674 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
FIG. 2 shows another cross-sectional view of the transis- tor of
FIG. 3 shows another cross-sectional view of the transis- tor of
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor comprising: a substrate layer; a buffer layer arranged on the substrate layer; a barrier layer arranged on the buffer layer; a drain arranged on the barrier layer; a gate arranged on the barrier layer; a source arranged on the barrier layer; the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to increase discharge efficiency and limit breakdown.
The high-electron mobility transistor of claim 1, wherein the length of the p-type material layer is configured and structured to retard an electric field, to increase electron confinement, and decrease leakage.
The high-electron mobility transistor of claim 1, further comprising: a plurality of unit cells; and the plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The high-electron mobility transistor of claim 1, further comprising: a p-type material contact arranged on and electrically coupled to the p-type material layer; and 30 a nucleation layer arranged on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The high-electron mobility transistor of claim 1, further comprising: 40 a recess in at least the barrier layer; the source comprises a p-type material contact arranged in the recess; and the p-type material contact is arranged on and electrically coupled to the p-type material layer.
The high-electron mobility transistor of claim 1, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The high-electron mobility transistor of claim 1, further comprising: a second buffer layer arranged on the buffer layer on a side of the buffer layer opposite of the substrate layer, wherein the barrier layer is arranged on the second buffer layer on a side opposite of the buffer layer.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The high-electron mobility transistor of claim 1, wherein the p-type material layer extends 60% to 80% of a B₂ gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
A process of making high-electron mobility transistor comprising: providing a substrate layer; arranging a buffer layer on the substrate layer; arranging a barrier layer arranged on the buffer layer; arranging a source on the barrier layer; arranging a drain on the barrier layer; arranging a gate on the barrier layer; configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an B₂ heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level; and arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer, wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to increase discharge efficiency and limit breakdown.
The process of making high-electron mobility tran-sistor of claim 9, further comprising configuring and struc-turing the length of the p-type material layer to retard an electric field, to increase electron confinement, and decrease leakage.
The process of making high-electron mobility tran-sistor of claim 9, further comprising providing a plurality of unit cells comprising a plurality of the gate, a plurality of the source, and a plurality of the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: arranging p-type material contact on and electrically coupled to the p-type material layer; and arranging a nucleation layer on the substrate layer and the buffer layer is arranged on the nucleation layer, wherein the substrate layer comprises Gallium Nitride; and wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the substrate layer to extend 0% to 50% of a distance between the gate and the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a recess in at least the barrier layer; and forming a source that comprises a portion having a p-type material contact arranged in the recess and the portion having the p-type material contact arranged on and electrically coupled to the p-type material layer; and arranging the p-type material contact on and electrically coupled to the p-type material layer.
The process of making high-electron mobility tran-sistor of claim 9, wherein the gate comprises a metal patterned to extend across a spacer layer such that a top of the gate forms a field plate arranged to extend a distance away from an edge of the gate towards the drain.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: providing a second buffer layer formed on the buffer layer; providing a protective layer formed on the barrier layer; and providing a nucleation layer arranged on the substrate layer, wherein the length of the p-type material layer is config-ured and structured parallel to the surface of the buffer layer to extend at least from the source past the gate and the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the buffer layer.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a nucleation layer on the substrate layer and arranging the buffer layer on the nucleation layer, wherein the substrate layer comprises Silicon Carbide.
The process of making high-electron mobility tran-sistor of claim 9, further comprising: forming a protective layer; arranging a gate in part on the barrier layer and in part on the protective layer; and forming a field plate structure extending a distance away from an edge of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a point within about 0 to about 0.3 µm of a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends to a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 0% to 20% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 20% to 40% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 40% to 60% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
The process of making high-electron mobility tran-sistor of claim 9, wherein the p-type material layer extends 60% to 80% of a gate length past a proximal edge of the gate; and wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
Layer stacks claimed or described, ordered top of device to substrate.
GaN high-electron mobility transistor (HEMT) with p-type layer
Materials described outside the worked examples.
p-type material layer
buffer layer
barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-sectional view of a transistor accord- ing to the principles of the disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.4–0.7 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 74
Related documents with shared materials, methods, properties, or citations.
two-dimensional electron gas (2DEG)
Gallium Nitride
GaN
Silicon Carbide
SiC
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
| — |
Thickness | 20–50 µm | — |
Temperature | 600–1050 °C | — |
Temperature | 950–1100 °C | — |
Duration | 30–600 s | — |
Thickness | 0–0.3 µm | — |
Temperature | 1300–1600 °C | — |
Temperature | 1200–1500 °C | — |
Temperature | 1440–1700 °C | — |
Temperature | 1200–1400 °C | — |
Cited non-patent literature · 8
two-dimensional electron gas (2DEG)
Gallium Nitride
GaN
Silicon Carbide
SiC
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
| — |
Thickness | 20–50 µm | — |
Temperature | 600–1050 °C | — |
Temperature | 950–1100 °C | — |
Duration | 30–600 s | — |
Thickness | 0–0.3 µm | — |
Temperature | 1300–1600 °C | — |
Temperature | 1200–1500 °C | — |
Temperature | 1440–1700 °C | — |
Temperature | 1200–1400 °C | — |
Cited non-patent literature · 8
two-dimensional electron gas (2DEG)
Gallium Nitride
GaN
Silicon Carbide
SiC
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
| — |
Thickness | 20–50 µm | — |
Temperature | 600–1050 °C | — |
Temperature | 950–1100 °C | — |
Duration | 30–600 s | — |
Thickness | 0–0.3 µm | — |
Temperature | 1300–1600 °C | — |
Temperature | 1200–1500 °C | — |
Temperature | 1440–1700 °C | — |
Temperature | 1200–1400 °C | — |
Cited non-patent literature · 8
two-dimensional electron gas (2DEG)
Gallium Nitride
GaN
Silicon Carbide
SiC
FIG. 4 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 5 shows a cross-sectional view of another aspect of a transistor according to principles of the disclosure.
FIG. 6 shows a process for making a transistor according to the principles of the disclosure.
| — |
Thickness | 20–50 µm | — |
Temperature | 600–1050 °C | — |
Temperature | 950–1100 °C | — |
Duration | 30–600 s | — |
Thickness | 0–0.3 µm | — |
Temperature | 1300–1600 °C | — |
Temperature | 1200–1500 °C | — |
Temperature | 1440–1700 °C | — |
Temperature | 1200–1400 °C | — |
Cited non-patent literature · 8