GRAPHENE CHANNEL-BASED DEVICES AND METHODS FOR FABRICATION THEREOF

Phaedon Avouris

Patent

Atlas literature

Patent

US 8,900,918

GRAPHENE CHANNEL-BASED DEVICES AND METHODS FOR FABRICATION THEREOF

Phaedon Avouris

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a cross-sectional diagram illustrating a graphene layer(s) having been deposited or grown on a substrate according to an embodiment of the present …

FIG. 2

FIG. 2 is a three-dimensional (3 D) diagram illustrating a top-down view of the graphene layer(s) on the substrate according to an embodiment of the present …

FIG. 3

FIG. 3 is a 3D diagram illustrating a mask having been formed over the graphene/substrate according to an embodiment of the present invention; [0015]

FIG. 4

FIG. 4 is a 3D diagram illustrating the graphene layer(s) having been etched around the mask to pattern and thus deﬁne channels according to an embodiment of …

FIG. 5

FIG. 5 is a cross-sectional diagram illustrating an oxide layer having been deposited over the patterned graphene layer(s) and substrate according to an …

FIG. 6

FIG. 6 is a cross-sectional diagram illustrating an etching mask having been formed over the oxide layer according to an embodiment of the present invention; …

FIG. 7

FIG. 7 is a cross-sectional diagram illustrating trenches having been etched into the oxide layer exposing underlying portions of graphene layer(s) according …

FIG. 8

FIG. 8 is a cross-sectional diagram illustrating metal having been deposited over the oxide layer ﬁlling the trenches according to an embodiment of the present …

FIG. 9

FIG. 9 is a cross-sectional diagram illustrating source and drain region metal contacts having been formed from the deposited metal according to an embodiment …

FIG. 10

FIG. 10 is a cross-sectional diagram illustrating a wafer-to-wafer bonding scheme being used to integrate the graphene wafer of

FIG. 11

FIG. 11 is a cross-sectional diagram illustrating the graphene wafer and the CMOS device wafer having been bonded together in a face-to-face manner using wafer …

FIG. 12

FIG. 12 is a cross-sectional diagram illustrating the substrate having been removed from the graphene wafer according to an embodiment of the present …

FIG. 13

FIG. 13 is a cross-sectional diagram illustrating the substrate having been removed from the CMOS device wafer according to an embodiment of the present …

FIG. 14

FIG. 14 is a cross-sectional diagram illustrating an additional metal layer having been added to the structure of

FIG. 15

FIG. 15 is a cross-sectional diagram illustrating an additional metal layer having been added to the structure shown in

FIG. 16

FIG. 16 is a cross-sectional diagram providing an example of how the CMOS device wafer components can be conﬁgured for integration with the graphene wafer …

FIG. 17

FIG. 17 is a cross-sectional diagram illustrating a graphene layer(s) having been deposited or grown on a substrate according to an embodiment of the present …

FIG. 18

FIG. 18 is a 3D diagram illustrating a top-down view of the graphene layer(s) having been deposited or grown on substrate according to an embodiment of the …

FIG. 19

FIG. 19 is a cross-sectional diagram illustrating a resist mask patterned over the graphene layer(s)/substrate according to an embodiment of the present …

FIG. 20

FIG. 20 is a 3D diagram illustrating a top-down view of the resist mask patterned over the graphene layer(s)/substrate according to an embodiment of the …

FIG. 21

FIG. 21 is a cross-sectional diagram illustrating source/drain contact metal having been deposited around the patterned resist mask according to an embodiment …

FIG. 22

FIG. 22 is a 3D diagram illustrating a top-down view of the source/drain contact metal having been deposited around the patterned resist mask according to an …

FIG. 23

FIG. 23 is a cross-sectional diagram illustrating a mask patterned on the graphene layer(s) to deﬁne an active channel region according to an embodiment of the …

FIG. 24

FIG. 24 is a 3D diagram illustrating a top-down view of the mask patterned on the graphene layer(s) according to an embodiment of the present invention; [0036]

FIG. 25

FIG. 25 is a cross-sectional diagram illustrating portions of the graphene layer(s) not protected by the mask having been etched away, and thus deﬁning a …

FIG. 26

FIG. 26 is a 3D diagram illustrating a top-down view of portions of the graphene layer(s) not protected by the mask having been etched away, and thus deﬁning a …

FIG. 27

FIG. 27 is a cross-sectional diagram illustrating a gate dielectric having been blanket deposited over the graphene channel, the source and drain metal …

FIG. 28

FIG. 28 is a 3D diagram illustrating a top-down view of the gate dielectric having been blanket deposited over the graphene channel, the source and drain metal …

FIG. 29

FIG. 29 is a cross-sectional diagram illustrating a gate metal contact patterned over the graphene channel and separated from the graphene channel by the gate …

FIG. 30

FIG. 30 is a 3D diagram illustrating a top-down view of the gate metal contact patterned over the graphene channel and separated from the graphene channel by …

FIG. 31

FIG. 31 is a cross-sectional diagram illustrating portions of the gate dielectric not covered by the gate metal contact having been etched away according to an …

FIG. 32

FIG. 32 is a 3D diagram illustrating a top-down view of the portions of the gate dielectric not covered by the gate metal contact having been etched away …

FIG. 33

FIG. 33 is a cross-sectional diagram illustrating a dopant having been blanket deposited over the source and drain metal contacts, the gate metal contact, …

FIG. 34

FIG. 34 is a 3D diagram illustrating a top-down view of the dopant having been blanket deposited over the source and drain metal contacts, the gate metal …

FIG. 35

FIG. 35 is a cross-sectional diagram illustrating a protective capping layer having been formed over the source and drain metal contacts, the gate metal …

FIG. 36

FIG. 36 is a 3D diagram illustrating a top-down view of the protective capping layer having been formed over the source and drain metal contacts, the gate …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

1 independent · 12 dependent

1
IndependentCoxide (gate dielectric/bonding oxide)graphene channel transistor bonded to CMOS device wafer
A method of fabricating a semiconductor device, comprising the steps of: forming a ﬁrst wafer having at least one graphene channel formed on a ﬁrst substrate, a ﬁrst oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the ﬁrst oxide layer; forming a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a-plurality-f contacts to the CMOS device layer that extend through the second oxide layer, the contacts to the CMOS device layer comprising at least one or more ﬁrst contacts to the CMOS device layer and at least one or more second contacts to the CMOS device layer; and bonding the ﬁ rst wafer and the second wafer together by way of an oxide-to-oxide bond directly between the ﬁrst and second oxide layers, such that the one or more ﬁrst ene-ermore of the contacts to the CMOS device layer are in contact with the source and drain contacts to the graphene channel, and the one or more second one or more-e ther of t he contacts to the CMOS device layer are gate contacts for the graphene channel, and wherein the ﬁrst oxide layer serves as a gate dielectric between the gate contacts and the graphene channel.
1. 2
  Dependent← claim 1
  The method of claim 1, f u rther comprising the step of: ﬂipping one of the ﬁrst wafer or the second wafer to permit face-to-face bonding with an other of the ﬁrst wafer or the second wafer.
2. 3
  Dependent← claim 1
  The method of claim 1, wherein the CMOS device layer comprises one or more CMOS wiring, structures and devices.
3. 4
  Dependent← claim 1
  The method of claim 1, wherein the ﬁrst substrate comprises an insulating wafer or a wafer having an insulating overlayer. 3 Docket No. YOR₉₂₀₀₈₀₆₂₅US₃ Customer No. 63919
4. 5
  Dependent← claim 1SiC
  The method of claim 1, wherein the ﬁrst substrate comprises a silicon carbide wafer.
5. 7
  Dependent← claim 1
  The method of claim 1, wherein the second substrate comprises a silicon-on-insulator wafer or a bulk silicon wafer.
6. 8
  Dependent← claim 1Cu
  The method of claim 1, wherein the source and drain contacts to the graphene channel and the contacts to the CMOS device layer each comprises copper, and wherein the ﬁrst wafer and the second wafer are further bonded together by way of a copper-to-copper bond between the source and drain contacts to the graphene channel and one or more of the contacts to the CMOS device layer.
7. 9
  Dependent← claim 1
  The method of claim 1, wherein the ﬁrst wafer and the second wafer are bonded together in a face-to-face orientation.
8. 10
  Dependent← claim 1Coxide (gate dielectric/bonding oxide)
  The method of claim 1, further comprising the st ep s tep s of: functionalizing a surface of the graphene channel; and depositing the ﬁrst oxide layer so as to surround the graphene channel.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

graphene channel transistor bonded to CMOS device wafer

gate contacts (from CMOS device layer via second oxide layer)gate contacts (from CMOS device layer via second oxide layer)

Cusource/drain contacts

oxide (gate dielectric/bonding oxide)gate dielectric / bonding oxide (first oxide layer)

Cgraphene channel

substrate (first wafer)substrate (first wafer)

graphene channel transistor with doped access regions

Materials

Materials described outside the worked examples.

graphene

Channel

oxide (gate dielectric/bonding oxide)

Gate Dielectric And Bonding Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Epitaxial Growth

Step 1

Process details

method:silicon carbide epitaxy/silicon sublimation with epitaxy

substrate:SiC wafer

Materials:CSiC

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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