Patent
US 9,472,684LATERAL GAN JFET WITH VERTICAL DRIFT REGION
Hui Nie, Andrew Edwards, Isik Kizilyalli, Dave Bour et al.
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,472,684Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A shows the lateral JFET turned off, which can be a default mode of operation (e.g., VG =0 V). As illustrated in
FIGS. 2-11 are simplified cross-sectional diagrams that illustrate a process for manufacturing a lateral JFET, according to one embodiment. [0009]
FIG. 3 shows how one or more portions of the blocking layer 230 can be removed to form one or more openings 310 in the blocking layer 230. The opening(s) 310 …
FIG. 4 illustrates the formation of a second GaN epitaxial layer 410 coupled to the blocking layer 230. The second GaN epitaxial layer 410, which eventually …
FIG. 5 illustrates the formation of a third GaN epitaxial layer 510 coupled to the second GaN epitaxial layer 410. The third GaN epitaxial layer 510 has a …
FIG. 6 illustrates the formation of an implanted region 610 formed in the second and third GaN epitaxial layers 410, 510. The implanted region 610 serves as a …
FIG. 7 illustrates the formation of a backside metal 710 can formed on a surface of the GaN substrate 210 opposing a surface of the GaN substrate 210 coupled …
FIG. 8 shows the formation of a p-ohmic metallization layer 810. P-ohmic metallization layer 810 can comprise one or more metals that makes a good Ohmic …
FIG. 9 illustrates the removal of a portion of the third GaN epitaxial layer 510 to form an opening 910. The removal process can also remove a portion of the …
FIG. 10 illustrates the formation of an opening 1010 in the implanted region 610 that can expose a surface of at least a portion of the blocking layer 230. The …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a lateral JFET, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
This application is in condition for allowance except for the presence of claims 8- 16 directed to an invention non-elected without traverse. Accordingly, claims 8-16 been cancelled.
Claims 1, 3-7, 17, 19 and 20 are allowed over the prior art.
The following is an examiner's statement of reasons for allowance: Allowable subject matter has been indicated because the closest prior reference of record, Zhao (U.S. Pub. Application 2003/0089930 A l), either alone or in combination, fails to teach or fairly suggest the feature inter alia (as amended), "a metal structure in direct contact with the source region and at least a portion of the blocking layer, the metal structure forming an ohmic contact with the source region." Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN JFET with vertical drift region
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,472,684Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A shows the lateral JFET turned off, which can be a default mode of operation (e.g., VG =0 V). As illustrated in
FIGS. 2-11 are simplified cross-sectional diagrams that illustrate a process for manufacturing a lateral JFET, according to one embodiment. [0009]
FIG. 3 shows how one or more portions of the blocking layer 230 can be removed to form one or more openings 310 in the blocking layer 230. The opening(s) 310 …
FIG. 4 illustrates the formation of a second GaN epitaxial layer 410 coupled to the blocking layer 230. The second GaN epitaxial layer 410, which eventually …
FIG. 5 illustrates the formation of a third GaN epitaxial layer 510 coupled to the second GaN epitaxial layer 410. The third GaN epitaxial layer 510 has a …
FIG. 6 illustrates the formation of an implanted region 610 formed in the second and third GaN epitaxial layers 410, 510. The implanted region 610 serves as a …
FIG. 7 illustrates the formation of a backside metal 710 can formed on a surface of the GaN substrate 210 opposing a surface of the GaN substrate 210 coupled …
FIG. 8 shows the formation of a p-ohmic metallization layer 810. P-ohmic metallization layer 810 can comprise one or more metals that makes a good Ohmic …
FIG. 9 illustrates the removal of a portion of the third GaN epitaxial layer 510 to form an opening 910. The removal process can also remove a portion of the …
FIG. 10 illustrates the formation of an opening 1010 in the implanted region 610 that can expose a surface of at least a portion of the blocking layer 230. The …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a lateral JFET, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
This application is in condition for allowance except for the presence of claims 8- 16 directed to an invention non-elected without traverse. Accordingly, claims 8-16 been cancelled.
Claims 1, 3-7, 17, 19 and 20 are allowed over the prior art.
The following is an examiner's statement of reasons for allowance: Allowable subject matter has been indicated because the closest prior reference of record, Zhao (U.S. Pub. Application 2003/0089930 A l), either alone or in combination, fails to teach or fairly suggest the feature inter alia (as amended), "a metal structure in direct contact with the source region and at least a portion of the blocking layer, the metal structure forming an ohmic contact with the source region." Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN JFET with vertical drift region
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,472,684Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A shows the lateral JFET turned off, which can be a default mode of operation (e.g., VG =0 V). As illustrated in
FIGS. 2-11 are simplified cross-sectional diagrams that illustrate a process for manufacturing a lateral JFET, according to one embodiment. [0009]
FIG. 3 shows how one or more portions of the blocking layer 230 can be removed to form one or more openings 310 in the blocking layer 230. The opening(s) 310 …
FIG. 4 illustrates the formation of a second GaN epitaxial layer 410 coupled to the blocking layer 230. The second GaN epitaxial layer 410, which eventually …
FIG. 5 illustrates the formation of a third GaN epitaxial layer 510 coupled to the second GaN epitaxial layer 410. The third GaN epitaxial layer 510 has a …
FIG. 6 illustrates the formation of an implanted region 610 formed in the second and third GaN epitaxial layers 410, 510. The implanted region 610 serves as a …
FIG. 7 illustrates the formation of a backside metal 710 can formed on a surface of the GaN substrate 210 opposing a surface of the GaN substrate 210 coupled …
FIG. 8 shows the formation of a p-ohmic metallization layer 810. P-ohmic metallization layer 810 can comprise one or more metals that makes a good Ohmic …
FIG. 9 illustrates the removal of a portion of the third GaN epitaxial layer 510 to form an opening 910. The removal process can also remove a portion of the …
FIG. 10 illustrates the formation of an opening 1010 in the implanted region 610 that can expose a surface of at least a portion of the blocking layer 230. The …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a lateral JFET, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
This application is in condition for allowance except for the presence of claims 8- 16 directed to an invention non-elected without traverse. Accordingly, claims 8-16 been cancelled.
Claims 1, 3-7, 17, 19 and 20 are allowed over the prior art.
The following is an examiner's statement of reasons for allowance: Allowable subject matter has been indicated because the closest prior reference of record, Zhao (U.S. Pub. Application 2003/0089930 A l), either alone or in combination, fails to teach or fairly suggest the feature inter alia (as amended), "a metal structure in direct contact with the source region and at least a portion of the blocking layer, the metal structure forming an ohmic contact with the source region." Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN JFET with vertical drift region
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,472,684Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A shows the lateral JFET turned off, which can be a default mode of operation (e.g., VG =0 V). As illustrated in
FIGS. 2-11 are simplified cross-sectional diagrams that illustrate a process for manufacturing a lateral JFET, according to one embodiment. [0009]
FIG. 3 shows how one or more portions of the blocking layer 230 can be removed to form one or more openings 310 in the blocking layer 230. The opening(s) 310 …
FIG. 4 illustrates the formation of a second GaN epitaxial layer 410 coupled to the blocking layer 230. The second GaN epitaxial layer 410, which eventually …
FIG. 5 illustrates the formation of a third GaN epitaxial layer 510 coupled to the second GaN epitaxial layer 410. The third GaN epitaxial layer 510 has a …
FIG. 6 illustrates the formation of an implanted region 610 formed in the second and third GaN epitaxial layers 410, 510. The implanted region 610 serves as a …
FIG. 7 illustrates the formation of a backside metal 710 can formed on a surface of the GaN substrate 210 opposing a surface of the GaN substrate 210 coupled …
FIG. 8 shows the formation of a p-ohmic metallization layer 810. P-ohmic metallization layer 810 can comprise one or more metals that makes a good Ohmic …
FIG. 9 illustrates the removal of a portion of the third GaN epitaxial layer 510 to form an opening 910. The removal process can also remove a portion of the …
FIG. 10 illustrates the formation of an opening 1010 in the implanted region 610 that can expose a surface of at least a portion of the blocking layer 230. The …
FIG. 12 is a simplified flowchart illustrating a method of fabricating a lateral JFET, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
This application is in condition for allowance except for the presence of claims 8- 16 directed to an invention non-elected without traverse. Accordingly, claims 8-16 been cancelled.
Claims 1, 3-7, 17, 19 and 20 are allowed over the prior art.
The following is an examiner's statement of reasons for allowance: Allowable subject matter has been indicated because the closest prior reference of record, Zhao (U.S. Pub. Application 2003/0089930 A l), either alone or in combination, fails to teach or fairly suggest the feature inter alia (as amended), "a metal structure in direct contact with the source region and at least a portion of the blocking layer, the metal structure forming an ohmic contact with the source region." Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN JFET with vertical drift region
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
| — |
Thickness | 200–4000 nm | — |
Thickness | 50–1000 nm | — |
Thickness | 500–1000 nm | — |
Voltage | ≥ 1 V | — |
METHOD FOR PREPARING GALLIUM NITRIDE (GAN) SINGLE-CRYSTAL SUBSTRATE WITH EDGE METAL MASK TECHNOLOGY
| — |
Thickness | 200–4000 nm | — |
Thickness | 50–1000 nm | — |
Thickness | 500–1000 nm | — |
Voltage | ≥ 1 V | — |
METHOD FOR PREPARING GALLIUM NITRIDE (GAN) SINGLE-CRYSTAL SUBSTRATE WITH EDGE METAL MASK TECHNOLOGY
| — |
Thickness | 200–4000 nm | — |
Thickness | 50–1000 nm | — |
Thickness | 500–1000 nm | — |
Voltage | ≥ 1 V | — |
METHOD FOR PREPARING GALLIUM NITRIDE (GAN) SINGLE-CRYSTAL SUBSTRATE WITH EDGE METAL MASK TECHNOLOGY
| — |
Thickness | 200–4000 nm | — |
Thickness | 50–1000 nm | — |
Thickness | 500–1000 nm | — |
Voltage | ≥ 1 V | — |
METHOD FOR PREPARING GALLIUM NITRIDE (GAN) SINGLE-CRYSTAL SUBSTRATE WITH EDGE METAL MASK TECHNOLOGY