Title: METHOD FOR DIRECTLY DEPOSITING PALLADIUM ONTO A NON-ACT IV ATED SURFACE OF A GALLIUM NITRIDE SEMICONDUCTOR

WALTER; c/o Atotech Deutsch- land GmbH

Patent

Atlas literature

Patent

US 10,920,322

Title: METHOD FOR DIRECTLY DEPOSITING PALLADIUM ONTO A NON-ACT IV ATED SURFACE OF A GALLIUM NITRIDE SEMICONDUCTOR

WALTER, Andreas

01 March 2018·US

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 17 dependent

1
IndependentGaNaqueous acidic palladium plating bathcompounds of formulae (I) and (II) — sulfonyl/sulfonamide heterocyclic additives
Method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor, comprising in this order the steps: (i) providing a doped or non-doped gallium nitride semiconductor with a non- activated surface, (ii) providing an aqueous, acidic palladium plating bath, comprising (a) Pd 2 + ions, (b) one or more than one reducing agent suitable to reduce Pd 2 + ions to metallic Pd 0, (c) one or more than one compound selected from the group consisting of compounds of formulae (I) and (II) SVG 16320123.02-14-2020.K₆MDUIVZRXEAPX2.CLM.1.svg 1.54 4.38 Black and white (I) (II), wherein R 1, R 2, R 3, R 4, R 5, R 6, R 7, and R 8 are independently H, alkyl, aryl, hetero aryl, NH2, S O 3H, or OH, and R 9 is independently H, alkyl, aryl, or hetero aryl, (iii) contacting the semiconductor with the plating bath such that metallic palladium or a palladium alloy is electrolessly deposited onto the non- activated surface of the semiconductor, the plating bath temperature being in the range of from 70 °C to 99 C. Original
1. 2
  Dependent← claim 1GaNaqueous acidic palladium plating bath
  Method according to claim 1, wherein the surface of the semiconductor is not contacted with or does not comprise Sn 2 + ions prior to step (iii) or when step (iii) is carried out. Previously presented
2. 3
  Dependent← claim 1GaNaqueous acidic palladium plating bath
  Method according to claim 1 comprising the additional step prior to step (111)-cleaning the non-activated surface with a cleaning solution, the cleaning solution comprising one or more than one ingredient selected from the group consisting of acids, bases, oxidizing agents, halogen ions, and organic solvents. Previously presented
3. 4
  Dependent← claim 1aqueous acidic palladium plating bath
  Method according to claim 1, wherein the pH of the acidic palladium plating bath is in the range of from 4.0 to 6.5. Previously presented
4. 5
  Dependent← claim 1compounds of formulae (I) and (II) — sulfonyl/sulfonamide heterocyclic additives
  Method according to claim 1, wherein (c) is one or more than one compound of formula (I),wherein R 1, R 2, R 3, and R 4 is H. Previously presented
5. 6
  Dependent← claim 1aqueous acidic palladium plating bath
  Method according to claim 1, wherein the palladium plating bath additionally contains (d) one or more than one complexing compound selected from amines. Currently amended
6. 7
  Dependent← claim 1GaNaqueous acidic palladium plating bath
  Method according to claim 1, wherein in step (iii) the semiconductor and the plating bath are in contact for 10 to 1200 seconds. Previously presented
7. 8
  Dependent← claim 1aqueous acidic palladium plating bath
  Method according to claim 1, wherein the plating bath temperature in step (iii) is in the range of from 70 °C to 95 C. Previously presented
8. 9
  Dependent← claim 1Pd
  Method according to claim 1, wherein the deposited palladium and palladium alloy has a total layer thickness in the range of from 10 nm to 1000 nm. Previously presented
9. 10
  Dependent← claim 1GaNPd
  Method according to claim 1, wherein the metallic palladium or palladium alloy is selectively deposited onto the non-activated surface such that a palladium pattern or palladium alloy pattern is obtained on the surface of the semiconductor. Previously presented
10. 11
  Dependent← claim 1Pd
  Method according to claim 1 comprising after step (iii) the additional step (iv) depositing an additional metal layer or metal alloy layer onto the electrolessly deposited metallic palladium/palladium alloy obtained after step (iii). Previously presented
11. 13
  Dependent← claim 1GaNPdpalladium or palladium alloy coated gallium nitride semiconductor
  Palladium or palladium alloy coated, doped or non-doped gallium nitride semiconductor obtained through the method deﬁned in claim 1. Withdrawn
12. 16
  Dependent← claim 1GaN
  Method according to claim 1, wherein the surface of the semiconductor is not contacted with or does not comprise activation metal ions or activation metal atoms prior to step (iii) or when step (iii) is carried out. Previously presented
13. 17
  Dependent← claim 1aqueous acidic palladium plating bath
  Method according to claim 1, wherein the pH of the acidic palladium plating bath is in the range of from 5.3 to 6.3. Previously presented
14. 18
  Dependent← claim 1saccharin salt
  Method according to claim 1, wherein the compound of formula (I) is a saccharin salt. Previously presented
15. 19
  Dependent← claim 1GaN
  Method according to claim 1, wherein the non- activated surface of the semiconductor in step (i) by itself does not reduce Pd 2+ ions to metallic Pd 0 or mediates the reduction of Pd 2+ ions to metallic Pd 0. Previously presented
16. 20
  Dependent← claim 1Pd
  Method according to claim 1 comprising after step (iii) the additional step (iv) depositing an additional metal layer or metal alloy layer onto the electrolessly deposited metallic palladium/palladium alloy obtained after step (iii) by electroless deposition. Previously presented
12
Independent
. Canceled
14
IndependentGaNPdpalladium or palladium alloy coated gallium nitride semiconductor
Palladium or palladium alloy coated, doped or non-doped gallium nitride semiconductor with an interface between the coated palladium or palladium alloy and the doped or non-doped gallium nitride semiconductor, wherein-the palladium and palladium alloy is wet chemically deposited, and-the interface does not contain tin ions, tin atoms, or tin containing compounds, and does not contain activation metal ions, activation metal atoms, or activation metal containing compounds. Withdrawn
1. 15
  Dependent← claim 14Pdpalladium or palladium alloy coated gallium nitride semiconductor
  Semiconductor according to claim 14, wherein the deposited palladium and palladium alloy has a total layer thickness in the range of from 10 nm to 1000 nm. Withdrawn

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

palladium or palladium alloy coated gallium nitride semiconductor

Pdmetal contact layer

GaNsubstrate

Materials

Materials described outside the worked examples.

gallium nitride semiconductor

GaN

Substrate Semiconductor

aqueous acidic palladium plating bath

Plating Bath

Process steps

Additional fabrication and treatment steps described in the patent.

Electroless Deposition

Step 1

Temperature

70, 99°C

Ambient

aqueous acidic bath

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Layer Thickness	10–1000 nm	Pd
Thickness	100–300 nm

Why these are connected

Related documents with shared materials, methods, properties, or citations.

Title: METHOD FOR DIRECTLY DEPOSITING PALLADIUM ONTO A NON-ACT IV ATED SURFACE OF A GALLIUM NITRIDE SEMICONDUCTOR | Matter42 Literature