Patent
Atlas literature
Patent
US 12,622,012 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional view of a conventional p-GaN single channel HEMT with a partially depleted 2 DEG channel;
FIG. 2B shows the second conventional approach of suppressing the formation of hot electrons and deterring the hot electrons from reaching the critical …
FIG. 3 is a cross-sectional view of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the present disclosure;
FIG. 4 is a side view of the p-GaN gate double channel HEMT of
FIG. 5 is an energy band diagram at VGS=0V of the p-GaN gate double channel HEMT of
FIGS. 6A-6G show various stages of an exemplary fab- rication process of the p-GaN gate double channel HEMT of
FIG. 7 is a flow diagram summarizing an exemplary fabrication process of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the …
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
FIGS. 9A and 9B show the transfer characteristics graphs of an exemplary p-GaN gate double channel HEMT in linear 5 scale and logarithmic scale;
FIGS. 10A and 10B show the output characteristics and the OFF-state characteristics of an exemplary p-GaN gate double channel HEMT;
FIG. 11A shows the comparison of the normalized 10 dynamic RON of a fresh unstressed single channel HEMT device and a fresh unstressed double channel HEMT …
FIG. 12B shows the schematic electron trajectories and simulated current distributions in a double channel HEMT 20 during semi-ON state;
FIG. 13B shows the current and lateral E-field distribution 25 along the upper channel near the drain-side gate corner in the double channel HEMT under hot …
FIG. 45 13B. Most hot electrons are generated in the lower channel layer 121. Extra scattering by the AlN of the ISL 122 and the GaN (the lower channel layer …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, comprising: a substrate; and a semiconductor stack formed on the substrate, compris-ing: a lower channel layer; an insertion layer (ISL) positioned above the lower chan-nel layer for confining electrons in the lower channel layer; an upper channel layer formed on the ISL and contacting the ISL; an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer; and a barrier layer positioned above the IEL, wherein: the ISL is formed above the lower channel layer to create a first wide bandgap heterojunction between the lower channel layer and the ISL; the IEL is formed above the upper channel layer to create a second wide bandgap heterojunction between the upper channel layer and the IEL; the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer, wherein the HEMT device further comprises a gate elec-trode, wherein the semiconductor stack further comprises a p-type cap that is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The HEMT device of claim 1, wherein the lower channel layer is selected from a group consisting GaN, InN, and their alloys; and the ISL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the upper channel layer is selected from a group consisting GaN, InN, and their alloys; and the IEL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the barrier layer is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the p-type cap is a layer of binary III-N compounds (AlN, GaN, InN), ternary III-N compounds (AlGaN, InAlN, InGaN), or qua-ternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the semicon-ductor stack further comprises a nucleation layer and a buffer layer, wherein the nucleation layer reduces a lattice mismatch between the substrate and the buffer layer; and the buffer layer isolates the nucleation layer from the lower channel layer.
A method for fabricating high electron mobility tran-sistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, the method comprising: preparing a substrate; and forming a semiconductor stack on the substrate, wherein forming the semiconductor stack comprises: forming a lower channel layer; forming an insertion layer (ISL) above the lower channel layer for confining electrons in the lower channel layer, thereby to create a first wide bandgap heterojunction between the lower channel layer and the ISL; forming an upper channel layer on the ISL, wherein the upper channel layer contacts the ISL; forming an interface enhancement layer (IEL) above the upper channel layer for confining the electrons in the upper channel layer, thereby to create a second wide bandgap heterojunction between the upper channel layer and the IEL; and B₂ forming a barrier layer above the IEL, wherein: the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer: wherein the method further comprises forming a gate electrode, wherein forming the semiconductor stack further com-prises: forming a p-type cap such that the p-type cap is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using material selected from binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using AlN, wherein the AlN is formed by MOCVD, MBE, HVPE, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD).
The method of claim 13, wherein forming the p-type cap further comprises: forming a p-type layer on the barrier layer by metal-organic chemical vapor deposition (MOCVD), molecu-lar beam epitaxy (MBE), or hydride vapour phase epitaxy (HVPE); and removing areas of the p-type layer to obtain the p-type cap by plasma dry etching, digital etching, or a combination thereof, wherein the method further comprises: depositing a passivation layer at the top of the barrier layer and the p-type cap; performing etching from the passivation layer at regions within the p-type cap to create a gate window, and at two opposing sides of the barrier layer to create a source window and a drain window; and depositing a plurality of ohmic contacts at the source window, the drain window, and the gate window to form a source electrode and a drain electrode on the barrier layer, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiNx, AlN/SiO2, and SiNx/SiO2.
The method of claim 13, wherein the step of forming the semiconductor stack further comprises performing depo-sition by MOCVD, MBE, or HVPE.
The method of claim 13 further comprising the step of forming pad metals for establishing connections to the source electrode, the gate electrode, and the drain electrode. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-off p-GaN gate double channel HEMT
Materials described outside the worked examples.
lower channel layer
insertion layer (ISL)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–3 µm | — |
Thickness | 1–2 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 22
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,622,012 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional view of a conventional p-GaN single channel HEMT with a partially depleted 2 DEG channel;
FIG. 2B shows the second conventional approach of suppressing the formation of hot electrons and deterring the hot electrons from reaching the critical …
FIG. 3 is a cross-sectional view of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the present disclosure;
FIG. 4 is a side view of the p-GaN gate double channel HEMT of
FIG. 5 is an energy band diagram at VGS=0V of the p-GaN gate double channel HEMT of
FIGS. 6A-6G show various stages of an exemplary fab- rication process of the p-GaN gate double channel HEMT of
FIG. 7 is a flow diagram summarizing an exemplary fabrication process of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the …
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
FIGS. 9A and 9B show the transfer characteristics graphs of an exemplary p-GaN gate double channel HEMT in linear 5 scale and logarithmic scale;
FIGS. 10A and 10B show the output characteristics and the OFF-state characteristics of an exemplary p-GaN gate double channel HEMT;
FIG. 11A shows the comparison of the normalized 10 dynamic RON of a fresh unstressed single channel HEMT device and a fresh unstressed double channel HEMT …
FIG. 12B shows the schematic electron trajectories and simulated current distributions in a double channel HEMT 20 during semi-ON state;
FIG. 13B shows the current and lateral E-field distribution 25 along the upper channel near the drain-side gate corner in the double channel HEMT under hot …
FIG. 45 13B. Most hot electrons are generated in the lower channel layer 121. Extra scattering by the AlN of the ISL 122 and the GaN (the lower channel layer …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, comprising: a substrate; and a semiconductor stack formed on the substrate, compris-ing: a lower channel layer; an insertion layer (ISL) positioned above the lower chan-nel layer for confining electrons in the lower channel layer; an upper channel layer formed on the ISL and contacting the ISL; an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer; and a barrier layer positioned above the IEL, wherein: the ISL is formed above the lower channel layer to create a first wide bandgap heterojunction between the lower channel layer and the ISL; the IEL is formed above the upper channel layer to create a second wide bandgap heterojunction between the upper channel layer and the IEL; the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer, wherein the HEMT device further comprises a gate elec-trode, wherein the semiconductor stack further comprises a p-type cap that is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The HEMT device of claim 1, wherein the lower channel layer is selected from a group consisting GaN, InN, and their alloys; and the ISL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the upper channel layer is selected from a group consisting GaN, InN, and their alloys; and the IEL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the barrier layer is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the p-type cap is a layer of binary III-N compounds (AlN, GaN, InN), ternary III-N compounds (AlGaN, InAlN, InGaN), or qua-ternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the semicon-ductor stack further comprises a nucleation layer and a buffer layer, wherein the nucleation layer reduces a lattice mismatch between the substrate and the buffer layer; and the buffer layer isolates the nucleation layer from the lower channel layer.
A method for fabricating high electron mobility tran-sistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, the method comprising: preparing a substrate; and forming a semiconductor stack on the substrate, wherein forming the semiconductor stack comprises: forming a lower channel layer; forming an insertion layer (ISL) above the lower channel layer for confining electrons in the lower channel layer, thereby to create a first wide bandgap heterojunction between the lower channel layer and the ISL; forming an upper channel layer on the ISL, wherein the upper channel layer contacts the ISL; forming an interface enhancement layer (IEL) above the upper channel layer for confining the electrons in the upper channel layer, thereby to create a second wide bandgap heterojunction between the upper channel layer and the IEL; and B₂ forming a barrier layer above the IEL, wherein: the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer: wherein the method further comprises forming a gate electrode, wherein forming the semiconductor stack further com-prises: forming a p-type cap such that the p-type cap is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using material selected from binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using AlN, wherein the AlN is formed by MOCVD, MBE, HVPE, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD).
The method of claim 13, wherein forming the p-type cap further comprises: forming a p-type layer on the barrier layer by metal-organic chemical vapor deposition (MOCVD), molecu-lar beam epitaxy (MBE), or hydride vapour phase epitaxy (HVPE); and removing areas of the p-type layer to obtain the p-type cap by plasma dry etching, digital etching, or a combination thereof, wherein the method further comprises: depositing a passivation layer at the top of the barrier layer and the p-type cap; performing etching from the passivation layer at regions within the p-type cap to create a gate window, and at two opposing sides of the barrier layer to create a source window and a drain window; and depositing a plurality of ohmic contacts at the source window, the drain window, and the gate window to form a source electrode and a drain electrode on the barrier layer, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiNx, AlN/SiO2, and SiNx/SiO2.
The method of claim 13, wherein the step of forming the semiconductor stack further comprises performing depo-sition by MOCVD, MBE, or HVPE.
The method of claim 13 further comprising the step of forming pad metals for establishing connections to the source electrode, the gate electrode, and the drain electrode. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-off p-GaN gate double channel HEMT
Materials described outside the worked examples.
lower channel layer
insertion layer (ISL)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–3 µm | — |
Thickness | 1–2 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 22
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,622,012 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional view of a conventional p-GaN single channel HEMT with a partially depleted 2 DEG channel;
FIG. 2B shows the second conventional approach of suppressing the formation of hot electrons and deterring the hot electrons from reaching the critical …
FIG. 3 is a cross-sectional view of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the present disclosure;
FIG. 4 is a side view of the p-GaN gate double channel HEMT of
FIG. 5 is an energy band diagram at VGS=0V of the p-GaN gate double channel HEMT of
FIGS. 6A-6G show various stages of an exemplary fab- rication process of the p-GaN gate double channel HEMT of
FIG. 7 is a flow diagram summarizing an exemplary fabrication process of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the …
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
FIGS. 9A and 9B show the transfer characteristics graphs of an exemplary p-GaN gate double channel HEMT in linear 5 scale and logarithmic scale;
FIGS. 10A and 10B show the output characteristics and the OFF-state characteristics of an exemplary p-GaN gate double channel HEMT;
FIG. 11A shows the comparison of the normalized 10 dynamic RON of a fresh unstressed single channel HEMT device and a fresh unstressed double channel HEMT …
FIG. 12B shows the schematic electron trajectories and simulated current distributions in a double channel HEMT 20 during semi-ON state;
FIG. 13B shows the current and lateral E-field distribution 25 along the upper channel near the drain-side gate corner in the double channel HEMT under hot …
FIG. 45 13B. Most hot electrons are generated in the lower channel layer 121. Extra scattering by the AlN of the ISL 122 and the GaN (the lower channel layer …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, comprising: a substrate; and a semiconductor stack formed on the substrate, compris-ing: a lower channel layer; an insertion layer (ISL) positioned above the lower chan-nel layer for confining electrons in the lower channel layer; an upper channel layer formed on the ISL and contacting the ISL; an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer; and a barrier layer positioned above the IEL, wherein: the ISL is formed above the lower channel layer to create a first wide bandgap heterojunction between the lower channel layer and the ISL; the IEL is formed above the upper channel layer to create a second wide bandgap heterojunction between the upper channel layer and the IEL; the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer, wherein the HEMT device further comprises a gate elec-trode, wherein the semiconductor stack further comprises a p-type cap that is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The HEMT device of claim 1, wherein the lower channel layer is selected from a group consisting GaN, InN, and their alloys; and the ISL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the upper channel layer is selected from a group consisting GaN, InN, and their alloys; and the IEL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the barrier layer is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the p-type cap is a layer of binary III-N compounds (AlN, GaN, InN), ternary III-N compounds (AlGaN, InAlN, InGaN), or qua-ternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the semicon-ductor stack further comprises a nucleation layer and a buffer layer, wherein the nucleation layer reduces a lattice mismatch between the substrate and the buffer layer; and the buffer layer isolates the nucleation layer from the lower channel layer.
A method for fabricating high electron mobility tran-sistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, the method comprising: preparing a substrate; and forming a semiconductor stack on the substrate, wherein forming the semiconductor stack comprises: forming a lower channel layer; forming an insertion layer (ISL) above the lower channel layer for confining electrons in the lower channel layer, thereby to create a first wide bandgap heterojunction between the lower channel layer and the ISL; forming an upper channel layer on the ISL, wherein the upper channel layer contacts the ISL; forming an interface enhancement layer (IEL) above the upper channel layer for confining the electrons in the upper channel layer, thereby to create a second wide bandgap heterojunction between the upper channel layer and the IEL; and B₂ forming a barrier layer above the IEL, wherein: the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer: wherein the method further comprises forming a gate electrode, wherein forming the semiconductor stack further com-prises: forming a p-type cap such that the p-type cap is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using material selected from binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using AlN, wherein the AlN is formed by MOCVD, MBE, HVPE, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD).
The method of claim 13, wherein forming the p-type cap further comprises: forming a p-type layer on the barrier layer by metal-organic chemical vapor deposition (MOCVD), molecu-lar beam epitaxy (MBE), or hydride vapour phase epitaxy (HVPE); and removing areas of the p-type layer to obtain the p-type cap by plasma dry etching, digital etching, or a combination thereof, wherein the method further comprises: depositing a passivation layer at the top of the barrier layer and the p-type cap; performing etching from the passivation layer at regions within the p-type cap to create a gate window, and at two opposing sides of the barrier layer to create a source window and a drain window; and depositing a plurality of ohmic contacts at the source window, the drain window, and the gate window to form a source electrode and a drain electrode on the barrier layer, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiNx, AlN/SiO2, and SiNx/SiO2.
The method of claim 13, wherein the step of forming the semiconductor stack further comprises performing depo-sition by MOCVD, MBE, or HVPE.
The method of claim 13 further comprising the step of forming pad metals for establishing connections to the source electrode, the gate electrode, and the drain electrode. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-off p-GaN gate double channel HEMT
Materials described outside the worked examples.
lower channel layer
insertion layer (ISL)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–3 µm | — |
Thickness | 1–2 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 22
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,622,012 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional view of a conventional p-GaN single channel HEMT with a partially depleted 2 DEG channel;
FIG. 2B shows the second conventional approach of suppressing the formation of hot electrons and deterring the hot electrons from reaching the critical …
FIG. 3 is a cross-sectional view of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the present disclosure;
FIG. 4 is a side view of the p-GaN gate double channel HEMT of
FIG. 5 is an energy band diagram at VGS=0V of the p-GaN gate double channel HEMT of
FIGS. 6A-6G show various stages of an exemplary fab- rication process of the p-GaN gate double channel HEMT of
FIG. 7 is a flow diagram summarizing an exemplary fabrication process of the p-GaN gate double channel HEMT, in accordance with certain embodiments of the …
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
FIGS. 9A and 9B show the transfer characteristics graphs of an exemplary p-GaN gate double channel HEMT in linear 5 scale and logarithmic scale;
FIGS. 10A and 10B show the output characteristics and the OFF-state characteristics of an exemplary p-GaN gate double channel HEMT;
FIG. 11A shows the comparison of the normalized 10 dynamic RON of a fresh unstressed single channel HEMT device and a fresh unstressed double channel HEMT …
FIG. 12B shows the schematic electron trajectories and simulated current distributions in a double channel HEMT 20 during semi-ON state;
FIG. 13B shows the current and lateral E-field distribution 25 along the upper channel near the drain-side gate corner in the double channel HEMT under hot …
FIG. 45 13B. Most hot electrons are generated in the lower channel layer 121. Extra scattering by the AlN of the ISL 122 and the GaN (the lower channel layer …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, comprising: a substrate; and a semiconductor stack formed on the substrate, compris-ing: a lower channel layer; an insertion layer (ISL) positioned above the lower chan-nel layer for confining electrons in the lower channel layer; an upper channel layer formed on the ISL and contacting the ISL; an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer; and a barrier layer positioned above the IEL, wherein: the ISL is formed above the lower channel layer to create a first wide bandgap heterojunction between the lower channel layer and the ISL; the IEL is formed above the upper channel layer to create a second wide bandgap heterojunction between the upper channel layer and the IEL; the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer, wherein the HEMT device further comprises a gate elec-trode, wherein the semiconductor stack further comprises a p-type cap that is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The HEMT device of claim 1, wherein the lower channel layer is selected from a group consisting GaN, InN, and their alloys; and the ISL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the upper channel layer is selected from a group consisting GaN, InN, and their alloys; and the IEL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the barrier layer is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the p-type cap is a layer of binary III-N compounds (AlN, GaN, InN), ternary III-N compounds (AlGaN, InAlN, InGaN), or qua-ternary III-N compounds (InAlGaN).
The HEMT device of claim 1, wherein the semicon-ductor stack further comprises a nucleation layer and a buffer layer, wherein the nucleation layer reduces a lattice mismatch between the substrate and the buffer layer; and the buffer layer isolates the nucleation layer from the lower channel layer.
A method for fabricating high electron mobility tran-sistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, the method comprising: preparing a substrate; and forming a semiconductor stack on the substrate, wherein forming the semiconductor stack comprises: forming a lower channel layer; forming an insertion layer (ISL) above the lower channel layer for confining electrons in the lower channel layer, thereby to create a first wide bandgap heterojunction between the lower channel layer and the ISL; forming an upper channel layer on the ISL, wherein the upper channel layer contacts the ISL; forming an interface enhancement layer (IEL) above the upper channel layer for confining the electrons in the upper channel layer, thereby to create a second wide bandgap heterojunction between the upper channel layer and the IEL; and B₂ forming a barrier layer above the IEL, wherein: the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer: wherein the method further comprises forming a gate electrode, wherein forming the semiconductor stack further com-prises: forming a p-type cap such that the p-type cap is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using material selected from binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
The method of claim 13, wherein the ISL, the IEL, and the barrier layer are fabricated using AlN, wherein the AlN is formed by MOCVD, MBE, HVPE, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD).
The method of claim 13, wherein forming the p-type cap further comprises: forming a p-type layer on the barrier layer by metal-organic chemical vapor deposition (MOCVD), molecu-lar beam epitaxy (MBE), or hydride vapour phase epitaxy (HVPE); and removing areas of the p-type layer to obtain the p-type cap by plasma dry etching, digital etching, or a combination thereof, wherein the method further comprises: depositing a passivation layer at the top of the barrier layer and the p-type cap; performing etching from the passivation layer at regions within the p-type cap to create a gate window, and at two opposing sides of the barrier layer to create a source window and a drain window; and depositing a plurality of ohmic contacts at the source window, the drain window, and the gate window to form a source electrode and a drain electrode on the barrier layer, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiNx, AlN/SiO2, and SiNx/SiO2.
The method of claim 13, wherein the step of forming the semiconductor stack further comprises performing depo-sition by MOCVD, MBE, or HVPE.
The method of claim 13 further comprising the step of forming pad metals for establishing connections to the source electrode, the gate electrode, and the drain electrode. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
normally-off p-GaN gate double channel HEMT
Materials described outside the worked examples.
lower channel layer
insertion layer (ISL)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a cross-sectional image of an exemplary p-GaN gate double channel HEMT captured by a transmission electron microscope (TEM);
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–3 µm | — |
Thickness | 1–2 µm |
Patents and literature cited by this patent (applicant and examiner references).
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Thickness | 100–500 nm | — |
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Thickness | 100–500 nm | — |
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Thickness | 10–20 nm | — |
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FIGS. 10A and 10B show the output characteristics and the OFF-state characteristics of an exemplary p-GaN gate double channel HEMT;
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Thickness | 100–500 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 2–10 nm | — |
Thickness | 10–20 nm | — |
Voltage | 0–8 V | — |
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