Patent
US 10,249,792PROTECTIVE CAPPING LAYER FOR SPALLED GALLIUM NITRIDE
Stephen W. Bedell
US
Copyright © 2026 Matter42. All rights reserved.
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US 10,249,792Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
FIG. 2 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at an early stage of device fabrication …
FIG. 3 is an enhanced cross sectional view of a Group III nitride region of
FIG. 4 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 5 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at a post-spalling stage of device …
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 7 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 8 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 9 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at later stage of device fabrication in …
FIG. 10 is a cross sectional view of an alternative embodiment of semiconductor device in accordance with present principles at a stage comparable to what is …
FIG. 11 is a block/flow diagram depicting the formation of a semiconductor device structure in accordance with an embodiment of the present principles.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of producing a semiconductor device comprising: forming a stack including a semiconductor material comprising: a Group III nitride semiconductor material formed on a growth substrate, a protective layer formed over the Group III nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer; and spalling the stack to separate the growth substrate from the stack. Original
The method of claim 1, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 1, f u rther comprising forming an adhesion layer between the protective layer and the stressor layer, the adhesion layer including a metal material that is applied to the protective layer by sputtering. Original
The method of claim 1, wherein the Group I II nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 1, wherein the Group III nitride material includes an n- doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
1 1. The method of claim 1, further comprising: forming a buffer layer between the growth substrate and the Group I II nitride semiconductor material; forming electrical contacts on a side of the Group III nitride semiconductor material; and removing the buffer layer before forming electrical contacts on the side of the Group III nitride semiconductor material. Original
A method of producing a semiconductor arrangement comprising: forming a stack including a semiconductor material comprising: a growth substrate, a buffer layer formed over the growth substrate, a Group III nitride semiconductor material formed over the buffer layer, a protective layer formed over the Group III nitride semiconductor material, a metal adhesion layer sputter-deposited over the protective layer, a stressor layer formed over the metal adhesion layer, and a handle layer formed over the stressor layer; spalling the stack to separate the growth substrate from the stack; and removing the buffer layer to expose a side of the Group III nitride semiconductor material. Original
The method of claim 12, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
The method of claim 12, wherein the protective layer includes a material selected the group consisting of aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide. Original
The method of claim 12, wherein the metal adhesion layer includes a metal material selected from the group consisting of titanium, tungsten, chromium, nickel and combinations thereof. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
spalled semiconductor device with Group III nitride
spalled semiconductor arrangement with buffer and adhesion layers
Materials described outside the worked examples.
Group III nitride semiconductor material
protective layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 650–850 °C | — |
Temperature | 850–1050 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,792Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
FIG. 2 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at an early stage of device fabrication …
FIG. 3 is an enhanced cross sectional view of a Group III nitride region of
FIG. 4 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 5 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at a post-spalling stage of device …
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 7 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 8 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 9 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at later stage of device fabrication in …
FIG. 10 is a cross sectional view of an alternative embodiment of semiconductor device in accordance with present principles at a stage comparable to what is …
FIG. 11 is a block/flow diagram depicting the formation of a semiconductor device structure in accordance with an embodiment of the present principles.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of producing a semiconductor device comprising: forming a stack including a semiconductor material comprising: a Group III nitride semiconductor material formed on a growth substrate, a protective layer formed over the Group III nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer; and spalling the stack to separate the growth substrate from the stack. Original
The method of claim 1, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 1, f u rther comprising forming an adhesion layer between the protective layer and the stressor layer, the adhesion layer including a metal material that is applied to the protective layer by sputtering. Original
The method of claim 1, wherein the Group I II nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 1, wherein the Group III nitride material includes an n- doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
1 1. The method of claim 1, further comprising: forming a buffer layer between the growth substrate and the Group I II nitride semiconductor material; forming electrical contacts on a side of the Group III nitride semiconductor material; and removing the buffer layer before forming electrical contacts on the side of the Group III nitride semiconductor material. Original
A method of producing a semiconductor arrangement comprising: forming a stack including a semiconductor material comprising: a growth substrate, a buffer layer formed over the growth substrate, a Group III nitride semiconductor material formed over the buffer layer, a protective layer formed over the Group III nitride semiconductor material, a metal adhesion layer sputter-deposited over the protective layer, a stressor layer formed over the metal adhesion layer, and a handle layer formed over the stressor layer; spalling the stack to separate the growth substrate from the stack; and removing the buffer layer to expose a side of the Group III nitride semiconductor material. Original
The method of claim 12, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
The method of claim 12, wherein the protective layer includes a material selected the group consisting of aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide. Original
The method of claim 12, wherein the metal adhesion layer includes a metal material selected from the group consisting of titanium, tungsten, chromium, nickel and combinations thereof. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
spalled semiconductor device with Group III nitride
spalled semiconductor arrangement with buffer and adhesion layers
Materials described outside the worked examples.
Group III nitride semiconductor material
protective layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 650–850 °C | — |
Temperature | 850–1050 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,792Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
FIG. 2 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at an early stage of device fabrication …
FIG. 3 is an enhanced cross sectional view of a Group III nitride region of
FIG. 4 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 5 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at a post-spalling stage of device …
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 7 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 8 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 9 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at later stage of device fabrication in …
FIG. 10 is a cross sectional view of an alternative embodiment of semiconductor device in accordance with present principles at a stage comparable to what is …
FIG. 11 is a block/flow diagram depicting the formation of a semiconductor device structure in accordance with an embodiment of the present principles.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of producing a semiconductor device comprising: forming a stack including a semiconductor material comprising: a Group III nitride semiconductor material formed on a growth substrate, a protective layer formed over the Group III nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer; and spalling the stack to separate the growth substrate from the stack. Original
The method of claim 1, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 1, f u rther comprising forming an adhesion layer between the protective layer and the stressor layer, the adhesion layer including a metal material that is applied to the protective layer by sputtering. Original
The method of claim 1, wherein the Group I II nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 1, wherein the Group III nitride material includes an n- doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
1 1. The method of claim 1, further comprising: forming a buffer layer between the growth substrate and the Group I II nitride semiconductor material; forming electrical contacts on a side of the Group III nitride semiconductor material; and removing the buffer layer before forming electrical contacts on the side of the Group III nitride semiconductor material. Original
A method of producing a semiconductor arrangement comprising: forming a stack including a semiconductor material comprising: a growth substrate, a buffer layer formed over the growth substrate, a Group III nitride semiconductor material formed over the buffer layer, a protective layer formed over the Group III nitride semiconductor material, a metal adhesion layer sputter-deposited over the protective layer, a stressor layer formed over the metal adhesion layer, and a handle layer formed over the stressor layer; spalling the stack to separate the growth substrate from the stack; and removing the buffer layer to expose a side of the Group III nitride semiconductor material. Original
The method of claim 12, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
The method of claim 12, wherein the protective layer includes a material selected the group consisting of aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide. Original
The method of claim 12, wherein the metal adhesion layer includes a metal material selected from the group consisting of titanium, tungsten, chromium, nickel and combinations thereof. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
spalled semiconductor device with Group III nitride
spalled semiconductor arrangement with buffer and adhesion layers
Materials described outside the worked examples.
Group III nitride semiconductor material
protective layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 650–850 °C | — |
Temperature | 850–1050 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,249,792Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
FIG. 2 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at an early stage of device fabrication …
FIG. 3 is an enhanced cross sectional view of a Group III nitride region of
FIG. 4 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 5 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at a post-spalling stage of device …
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 7 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 8 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
FIG. 9 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at later stage of device fabrication in …
FIG. 10 is a cross sectional view of an alternative embodiment of semiconductor device in accordance with present principles at a stage comparable to what is …
FIG. 11 is a block/flow diagram depicting the formation of a semiconductor device structure in accordance with an embodiment of the present principles.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of producing a semiconductor device comprising: forming a stack including a semiconductor material comprising: a Group III nitride semiconductor material formed on a growth substrate, a protective layer formed over the Group III nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer; and spalling the stack to separate the growth substrate from the stack. Original
The method of claim 1, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 1, f u rther comprising forming an adhesion layer between the protective layer and the stressor layer, the adhesion layer including a metal material that is applied to the protective layer by sputtering. Original
The method of claim 1, wherein the Group I II nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 1, wherein the Group III nitride material includes an n- doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
1 1. The method of claim 1, further comprising: forming a buffer layer between the growth substrate and the Group I II nitride semiconductor material; forming electrical contacts on a side of the Group III nitride semiconductor material; and removing the buffer layer before forming electrical contacts on the side of the Group III nitride semiconductor material. Original
A method of producing a semiconductor arrangement comprising: forming a stack including a semiconductor material comprising: a growth substrate, a buffer layer formed over the growth substrate, a Group III nitride semiconductor material formed over the buffer layer, a protective layer formed over the Group III nitride semiconductor material, a metal adhesion layer sputter-deposited over the protective layer, a stressor layer formed over the metal adhesion layer, and a handle layer formed over the stressor layer; spalling the stack to separate the growth substrate from the stack; and removing the buffer layer to expose a side of the Group III nitride semiconductor material. Original
The method of claim 12, further comprising vertically extending portions of the stressor layer along the sides of the stack that extend to the growth substrate. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped region, a multiple quantum well region and a p-doped region, the protective layer being formed directly on top of the p-doped region. Original
The method of claim 12, wherein the Group III nitride material includes an n-doped gallium nitride region, a multiple quantum well region including gallium nitride and indium-gallium nitride, and a p-doped gallium nitride region, the protective layer being formed directly on top of the p-doped gallium nitride region. Original
The method of claim 12, wherein the protective layer includes a material selected the group consisting of aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide. Original
The method of claim 12, wherein the metal adhesion layer includes a metal material selected from the group consisting of titanium, tungsten, chromium, nickel and combinations thereof. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
spalled semiconductor device with Group III nitride
spalled semiconductor arrangement with buffer and adhesion layers
Materials described outside the worked examples.
Group III nitride semiconductor material
protective layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional view of what is observed in a transmission electron microscopy (TEM) image of a GaN semiconductor device that has been damaged …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 650–850 °C | — |
Temperature | 850–1050 °C |
Related documents with shared materials, methods, properties, or citations.
stressor layer
metal adhesion layer
adhesion layer metal selected from titanium, tungsten, chromium, nickel and combinations thereof
n-doped gallium nitride
GaN
indium-gallium nitride (MQW region)
InGaN
protective layer material selected from aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide
titanium adhesion layer
Ti
buffer layer
p-doped gallium nitride
GaN:Mg
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
| — |
Duration | 1–20 minutes | — |
Temperature | 900–1200 °C | — |
Temperature | 1200–1400 °C | — |
Duration | 60–7200 s | — |
Temperature | 500–700 °C | — |
Thickness | 5–200 nm | — |
Thickness | 100–150 nm | — |
Thickness | 5–50 um | — |
Temperature | 15–40 °C | — |
Temperature | 15–60 °C | — |
Temperature | 130–175 K | — |
Thickness | 100–3000 µm | — |
Thickness | 5–500 nm | — |
Thickness | ≤ 1 nm | — |
Temperature | ≤ 700 °C | — |
Thickness | ≤ 30 cm | — |
Temperature | ≤ 20 °C | — |
Temperature | ≤ 206 K | — |
METHOD OF FABRICATING SLANTED FIELD-PLATE GAN HETEROJUNCTION FIELD-EFFECT TRANSISTOR
stressor layer
metal adhesion layer
adhesion layer metal selected from titanium, tungsten, chromium, nickel and combinations thereof
n-doped gallium nitride
GaN
indium-gallium nitride (MQW region)
InGaN
protective layer material selected from aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide
titanium adhesion layer
Ti
buffer layer
p-doped gallium nitride
GaN:Mg
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
| — |
Duration | 1–20 minutes | — |
Temperature | 900–1200 °C | — |
Temperature | 1200–1400 °C | — |
Duration | 60–7200 s | — |
Temperature | 500–700 °C | — |
Thickness | 5–200 nm | — |
Thickness | 100–150 nm | — |
Thickness | 5–50 um | — |
Temperature | 15–40 °C | — |
Temperature | 15–60 °C | — |
Temperature | 130–175 K | — |
Thickness | 100–3000 µm | — |
Thickness | 5–500 nm | — |
Thickness | ≤ 1 nm | — |
Temperature | ≤ 700 °C | — |
Thickness | ≤ 30 cm | — |
Temperature | ≤ 20 °C | — |
Temperature | ≤ 206 K | — |
METHOD OF FABRICATING SLANTED FIELD-PLATE GAN HETEROJUNCTION FIELD-EFFECT TRANSISTOR
stressor layer
metal adhesion layer
adhesion layer metal selected from titanium, tungsten, chromium, nickel and combinations thereof
n-doped gallium nitride
GaN
indium-gallium nitride (MQW region)
InGaN
protective layer material selected from aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide
titanium adhesion layer
Ti
buffer layer
p-doped gallium nitride
GaN:Mg
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
| — |
Duration | 1–20 minutes | — |
Temperature | 900–1200 °C | — |
Temperature | 1200–1400 °C | — |
Duration | 60–7200 s | — |
Temperature | 500–700 °C | — |
Thickness | 5–200 nm | — |
Thickness | 100–150 nm | — |
Thickness | 5–50 um | — |
Temperature | 15–40 °C | — |
Temperature | 15–60 °C | — |
Temperature | 130–175 K | — |
Thickness | 100–3000 µm | — |
Thickness | 5–500 nm | — |
Thickness | ≤ 1 nm | — |
Temperature | ≤ 700 °C | — |
Thickness | ≤ 30 cm | — |
Temperature | ≤ 20 °C | — |
Temperature | ≤ 206 K | — |
METHOD OF FABRICATING SLANTED FIELD-PLATE GAN HETEROJUNCTION FIELD-EFFECT TRANSISTOR
stressor layer
metal adhesion layer
adhesion layer metal selected from titanium, tungsten, chromium, nickel and combinations thereof
n-doped gallium nitride
GaN
indium-gallium nitride (MQW region)
InGaN
protective layer material selected from aluminum nitride, gallium nitride, silicon nitride, and aluminum oxide
titanium adhesion layer
Ti
buffer layer
p-doped gallium nitride
GaN:Mg
FIG. 6 is a cross sectional view of a semiconductor device in accordance with an embodiment of the present principles at another stage of device fabrication in …
| — |
Duration | 1–20 minutes | — |
Temperature | 900–1200 °C | — |
Temperature | 1200–1400 °C | — |
Duration | 60–7200 s | — |
Temperature | 500–700 °C | — |
Thickness | 5–200 nm | — |
Thickness | 100–150 nm | — |
Thickness | 5–50 um | — |
Temperature | 15–40 °C | — |
Temperature | 15–60 °C | — |
Temperature | 130–175 K | — |
Thickness | 100–3000 µm | — |
Thickness | 5–500 nm | — |
Thickness | ≤ 1 nm | — |
Temperature | ≤ 700 °C | — |
Thickness | ≤ 30 cm | — |
Temperature | ≤ 20 °C | — |
Temperature | ≤ 206 K | — |
METHOD OF FABRICATING SLANTED FIELD-PLATE GAN HETEROJUNCTION FIELD-EFFECT TRANSISTOR