Patent
US 9,985,121P-Type Diamond Gate-GaN Heterojunction FET Structure
Kenneth R. Elliott
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,985,121Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A F ET device comprising: a substrate having top and bottom surfaces; a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; at least two recesses extending into the channel layer from the top surface of the channel layer, extending through the bottom surface of the channel layer, and forming a channel region between the at least two recesses; a gate electrode disposed in each of the at least two recesses; and a drain region and a source region formed in the channel layer on opposite sides of said channel region; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The FET device of claim 1, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The FET device of claim 1, wherein a conductor is arranged above the channel layer and connects the gate electrodes disposed within each of the at least two recesses to form a single gate electrode. Original
The FET device of claim 1: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The FET device of claim 1, wherein the channel layer is separated from the gate electrode by a capping layer. Original
The FET device of claim 1: wherein the channel layer is separated from the substrate by a buffer layer; and wherein the junction of the buffer layer and the channel layer forms a heterojunction. Original
The FET device of claim 1, comprising insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions. Original
The F ET device of claim 1, comprising Ohmic contacts to the source and drain regions. Original
The F ET device of claim 1 further comprising: a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The FET device of claim 1 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
A method of fabricating a FET device comprising: forming a substrate having top and bottom surfaces; forming a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; forming at least two recesses extending into the channel layer from the top surface of the channel layer and extending through the bottom surface of the channel layer, thus forming a channel region between the at least two recesses and forming a drain region and a source region in the channel layer on opposite sides of said channel region; and forming a gate electrode in each of the at least two recesses; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The method of claim 14, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The method of claim 14, comprising arranging a conductor above the channel layer so as to connect the conductor material in the at least two recesses to form a single gate electrode. Original
The method of claim 14: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The method of claim 14, comprising growing a capping layer to separate the channel layer from the gate electrode. Original
The method of claim 14, comprising growing a buffer layer on the substrate prior to growing the channel layer on the buffer layer; the junction of the buffer layer and the channel layer forming a heterojunction. Original
The method of claim 14, comprising: forming insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions; wherein forming said insulating regions comprises etching recesses in the channel layer or forming said insulating regions comprises ion implantation. Original
The method of claim 14 further comprising: forming a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The method of claim 14 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
29-30. Cancelled Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-type diamond gate GaN heterojunction FET
p-type diamond gate GaN FET with superlattice channel
Materials described outside the worked examples.
p-type diamond
channel layer material (unspecified)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,985,121Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A F ET device comprising: a substrate having top and bottom surfaces; a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; at least two recesses extending into the channel layer from the top surface of the channel layer, extending through the bottom surface of the channel layer, and forming a channel region between the at least two recesses; a gate electrode disposed in each of the at least two recesses; and a drain region and a source region formed in the channel layer on opposite sides of said channel region; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The FET device of claim 1, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The FET device of claim 1, wherein a conductor is arranged above the channel layer and connects the gate electrodes disposed within each of the at least two recesses to form a single gate electrode. Original
The FET device of claim 1: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The FET device of claim 1, wherein the channel layer is separated from the gate electrode by a capping layer. Original
The FET device of claim 1: wherein the channel layer is separated from the substrate by a buffer layer; and wherein the junction of the buffer layer and the channel layer forms a heterojunction. Original
The FET device of claim 1, comprising insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions. Original
The F ET device of claim 1, comprising Ohmic contacts to the source and drain regions. Original
The F ET device of claim 1 further comprising: a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The FET device of claim 1 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
A method of fabricating a FET device comprising: forming a substrate having top and bottom surfaces; forming a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; forming at least two recesses extending into the channel layer from the top surface of the channel layer and extending through the bottom surface of the channel layer, thus forming a channel region between the at least two recesses and forming a drain region and a source region in the channel layer on opposite sides of said channel region; and forming a gate electrode in each of the at least two recesses; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The method of claim 14, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The method of claim 14, comprising arranging a conductor above the channel layer so as to connect the conductor material in the at least two recesses to form a single gate electrode. Original
The method of claim 14: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The method of claim 14, comprising growing a capping layer to separate the channel layer from the gate electrode. Original
The method of claim 14, comprising growing a buffer layer on the substrate prior to growing the channel layer on the buffer layer; the junction of the buffer layer and the channel layer forming a heterojunction. Original
The method of claim 14, comprising: forming insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions; wherein forming said insulating regions comprises etching recesses in the channel layer or forming said insulating regions comprises ion implantation. Original
The method of claim 14 further comprising: forming a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The method of claim 14 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
29-30. Cancelled Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-type diamond gate GaN heterojunction FET
p-type diamond gate GaN FET with superlattice channel
Materials described outside the worked examples.
p-type diamond
channel layer material (unspecified)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,985,121Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A F ET device comprising: a substrate having top and bottom surfaces; a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; at least two recesses extending into the channel layer from the top surface of the channel layer, extending through the bottom surface of the channel layer, and forming a channel region between the at least two recesses; a gate electrode disposed in each of the at least two recesses; and a drain region and a source region formed in the channel layer on opposite sides of said channel region; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The FET device of claim 1, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The FET device of claim 1, wherein a conductor is arranged above the channel layer and connects the gate electrodes disposed within each of the at least two recesses to form a single gate electrode. Original
The FET device of claim 1: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The FET device of claim 1, wherein the channel layer is separated from the gate electrode by a capping layer. Original
The FET device of claim 1: wherein the channel layer is separated from the substrate by a buffer layer; and wherein the junction of the buffer layer and the channel layer forms a heterojunction. Original
The FET device of claim 1, comprising insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions. Original
The F ET device of claim 1, comprising Ohmic contacts to the source and drain regions. Original
The F ET device of claim 1 further comprising: a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The FET device of claim 1 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
A method of fabricating a FET device comprising: forming a substrate having top and bottom surfaces; forming a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; forming at least two recesses extending into the channel layer from the top surface of the channel layer and extending through the bottom surface of the channel layer, thus forming a channel region between the at least two recesses and forming a drain region and a source region in the channel layer on opposite sides of said channel region; and forming a gate electrode in each of the at least two recesses; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The method of claim 14, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The method of claim 14, comprising arranging a conductor above the channel layer so as to connect the conductor material in the at least two recesses to form a single gate electrode. Original
The method of claim 14: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The method of claim 14, comprising growing a capping layer to separate the channel layer from the gate electrode. Original
The method of claim 14, comprising growing a buffer layer on the substrate prior to growing the channel layer on the buffer layer; the junction of the buffer layer and the channel layer forming a heterojunction. Original
The method of claim 14, comprising: forming insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions; wherein forming said insulating regions comprises etching recesses in the channel layer or forming said insulating regions comprises ion implantation. Original
The method of claim 14 further comprising: forming a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The method of claim 14 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
29-30. Cancelled Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-type diamond gate GaN heterojunction FET
p-type diamond gate GaN FET with superlattice channel
Materials described outside the worked examples.
p-type diamond
channel layer material (unspecified)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,985,121Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A F ET device comprising: a substrate having top and bottom surfaces; a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; at least two recesses extending into the channel layer from the top surface of the channel layer, extending through the bottom surface of the channel layer, and forming a channel region between the at least two recesses; a gate electrode disposed in each of the at least two recesses; and a drain region and a source region formed in the channel layer on opposite sides of said channel region; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The FET device of claim 1, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The FET device of claim 1, wherein a conductor is arranged above the channel layer and connects the gate electrodes disposed within each of the at least two recesses to form a single gate electrode. Original
The FET device of claim 1: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The FET device of claim 1, wherein the channel layer is separated from the gate electrode by a capping layer. Original
The FET device of claim 1: wherein the channel layer is separated from the substrate by a buffer layer; and wherein the junction of the buffer layer and the channel layer forms a heterojunction. Original
The FET device of claim 1, comprising insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions. Original
The F ET device of claim 1, comprising Ohmic contacts to the source and drain regions. Original
The F ET device of claim 1 further comprising: a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The FET device of claim 1 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
A method of fabricating a FET device comprising: forming a substrate having top and bottom surfaces; forming a channel layer on the top surface of the substrate, the channel layer having top and bottom surfaces; forming at least two recesses extending into the channel layer from the top surface of the channel layer and extending through the bottom surface of the channel layer, thus forming a channel region between the at least two recesses and forming a drain region and a source region in the channel layer on opposite sides of said channel region; and forming a gate electrode in each of the at least two recesses; wherein each gate electrode comprises a p-type diamond gate. Currently amended
The method of claim 14, wherein the channel region extends from the top surface to the bottom surface of the channel layer. Original
The method of claim 14, comprising arranging a conductor above the channel layer so as to connect the conductor material in the at least two recesses to form a single gate electrode. Original
The method of claim 14: wherein the channel layer material comprises a wide bandgap material or comprises a III- N material. Previously presented
The method of claim 14, comprising growing a capping layer to separate the channel layer from the gate electrode. Original
The method of claim 14, comprising growing a buffer layer on the substrate prior to growing the channel layer on the buffer layer; the junction of the buffer layer and the channel layer forming a heterojunction. Original
The method of claim 14, comprising: forming insulating regions along the walls of the at least two recesses, between the at least two recesses and the source and drain regions; wherein forming said insulating regions comprises etching recesses in the channel layer or forming said insulating regions comprises ion implantation. Original
The method of claim 14 further comprising: forming a barrier layer on the top surface of the channel layer; wherein the at least two recesses extend through the barrier layer. Previously presented
The method of claim 14 wherein each p-type diamond gate comprises Boron-doped Nano Crystalline Diamond (NCD). Previously presented
29-30. Cancelled Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
p-type diamond gate GaN heterojunction FET
p-type diamond gate GaN FET with superlattice channel
Materials described outside the worked examples.
p-type diamond
channel layer material (unspecified)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
wide bandgap material/III-N material
GaN
InGaN
AlGaN
AlN
SiC
Boron-doped Nano Crystalline Diamond (NCD)
Al0.08Ga0.92N buffer layer
Al0.08Ga0.92N
Al0.5Ga0.5N cap layer
Al0.5Ga0.5N
boron-doped diamond
boron-doped silicon carbide
gold gate contact
Au
wide bandgap material/III-N material
GaN
InGaN
AlGaN
AlN
SiC
Boron-doped Nano Crystalline Diamond (NCD)
Al0.08Ga0.92N buffer layer
Al0.08Ga0.92N
Al0.5Ga0.5N cap layer
Al0.5Ga0.5N
boron-doped diamond
boron-doped silicon carbide
gold gate contact
Au
wide bandgap material/III-N material
GaN
InGaN
AlGaN
AlN
SiC
Boron-doped Nano Crystalline Diamond (NCD)
Al0.08Ga0.92N buffer layer
Al0.08Ga0.92N
Al0.5Ga0.5N cap layer
Al0.5Ga0.5N
boron-doped diamond
boron-doped silicon carbide
gold gate contact
Au
wide bandgap material/III-N material
GaN
InGaN
AlGaN
AlN
SiC
Boron-doped Nano Crystalline Diamond (NCD)
Al0.08Ga0.92N buffer layer
Al0.08Ga0.92N
Al0.5Ga0.5N cap layer
Al0.5Ga0.5N
boron-doped diamond
boron-doped silicon carbide
gold gate contact
Au