SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Taishi ISHIKURA

Patent

Atlas literature

Patent

US 9,484,206

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Taishi ISHIKURA

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device of a ﬁrst embodiment;

FIG. 2

FIG. 2 is a cross-sectional view for explaining a method for manufacturing the semiconductor device of 35 the ﬁrst embodiment;

FIG. 3

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device-2-of the ﬁrst embodiment, following

FIG. 4

FIG. 4B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment;

FIG. 5

FIG. 5 B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment, following

FIG. 6

FIG. 6B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment, following

FIG. 7

FIG. 7B is a cross-sectional view for explaining the method for manufacturing the semiconductor device 25 of the second embodiment, following

FIG. 8

FIG. 8 B is a cross-sectional view for explaining 30 the method for manufacturing the semiconductor device of the second embodiment, following

FIG. 9

FIG. 9B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment;-3 -

FIG. 10

FIG. 10 B is a plan view for explaining the method 5 for manufacturing the semiconductor device of the third embodiment, following

FIG. 11

FIG. 11 B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment, following

FIG. 12

FIG. 12B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment, following

FIG. 13

FIG. 13B is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment, following

FIG. 14

FIG. 14 is a cross-sectional view for explaining a method for manufacturing a semiconductor device of a fourth embodiment;

FIG. 15

FIG. 15 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 30 of the fourth embodiment, following

FIG. 16

FIG. 16 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the fourth embodiment, following

FIG. 17

FIG. 17 is a cross-sectional view for explaining 35 the method for manufacturing the semiconductor device of the fourth embodiment, following

FIG. 18

FIG. 18 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the fourth embodiment, following

FIG. 19

FIG. 19 is a cross-sectional view for explaining a method for manufacturing another semiconductor device 5 of the fourth embodiment;

FIG. 20

FIG. 20 is a cross-sectional view for explaining the method for manufacturing the another semiconductor device of the fourth embodiment, following

FIG. 21

FIG. 21 is a cross-sectional view for explaining 10 the method for manufacturing the another semiconductor device of the fourth embodiment, following

FIG. 22

FIG. 22 is a cross-sectional view for explaining the method for manufacturing the another semiconductor device of t he fourth embodiment, following

FIG. 23

FIG. 23 is a cross- sectional view for explaining the method for manufacturing the another semiconductor device of the fourth embodiment, following

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

5 independent · 16 dependent

1
Independentfirst aggregation layer materialsecond aggregation layer materialCsemiconductor device with foundation layer and graphene interconnect
A semiconductor device comprising: a foundation layer including ﬁrst and second layers being diﬀerent from each other in material, [[and]] the foundation layer including a surface on which a boundary of the ﬁrst and second layers is presented; a catalyst layer on the surface of the foundation layer, [[and]] the catalyst layer including a protruding area, and an edge portion of the protruding area or a part of the protruding area except the edge portion being disposed directly above the boundary of the ﬁrst and second layers; and a graphene layer bcing in contact with the protruding area.
1. 3
  Dependent← claim 1first aggregation layer materialsecond aggregation layer materialCsemiconductor device with foundation layer and graphene interconnect
  The device according to claim 1, wherein the catalyst layer is on the ﬁrst and second layers.
2. 13
  Dependent← claim 1first aggregation layer materialsecond aggregation layer materialCsemiconductor device with foundation layer and graphene interconnect
  The device according to claim 1, wherein the second layer promotes aggregation of the catalyst layer more than the ﬁrst aggregation layer does.
3. 14
  Dependent← claim 1first aggregation layer materialsecond aggregation layer materialCsemiconductor device with foundation layer and graphene interconnect
  The device according to claim 1, wherein a material of the ﬁrst layer includes Cr, Tc, Ru, Os, Re, C, Pd, Pt, Rh, Ir, Cd, or W; a material of the second layer includes Ti, TiN, Ta, or TaN; and a material of the catalyst layer includes Ni, C o, Fe, or Cu.
4. 16
  Dependent← claim 1Csemiconductor device with foundation layer and graphene interconnect
  The device according to claim 1, wherein the graphene layer constitutes an interconnect.
5. 21
  Dependent← claim 1
  The device according to claim 1, wherein the from both a ﬁrst edge portion of the catalyst layer and the ﬁrst edge portion and the second edge
6. 22
  Dependent← claim 1
  The device according to claim 1, wherein the of the protruding area except the edge portion, layers when viewed from a direction perpendicular protruding area of the catalyst layer is away and a second edge portion of the catalyst layer, portion are opposite to each other. edge portion of the protruding area, or the part overlaps the boundary of the ﬁrst and second to the surface of the foundation la y er.
2
Independent
canceled
8
Dependent← claim 7second aggregation layer materialCsemiconductor device with insulating film trench and graphene layer
The device according to claim 7, wherein the catalyst layer is selectively on the ﬁrst layer.
1. 9
  Dependent← claim 8second aggregation layer materialCalloy of first layer material and catalyst layer materialsemiconductor device with insulating film trench and graphene layer
  The device according to claim 8, further comprising an alloy layer on the second la y er outside the trench.
17
Independentsecond aggregation layer materialCinsulating filmsemiconductor device with insulating film trench and graphene layer
A semiconductor device comprising: an insulating ﬁlm including a surface and a trench in the surface; a catalyst layer on the surface, the catalyst layer including a ﬁrst portion which is on a bottom of the trench and a second portion which is outside the trench, the ﬁrst portion having a ﬁrst thickness larger than a depth of the trench, and the second portion having a second thickness smaller than the ﬁrst thickness; and a graphene layer on the catalyst layer.
1. 18
  Dependent← claim 17Csemiconductor device with insulating film trench and graphene layer
  The device according to claim 17, wherein the graphene layer constitutes an alignment mark.
19
Independent
Claims 19 and 20. canceled
20
Independent
canceled

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor device with foundation layer and graphene interconnect

Cgraphene layer

catalyst layer material (Ni, Co, Fe, or Cu)catalyst layer with protruding area

second aggregation layer materialfoundation second layer

first aggregation layer materialfoundation first layer

semiconductor device with insulating film trench and graphene layer

Cgraphene layer

Materials

Materials described outside the worked examples.

first aggregation layer material

Foundation First Layer

Cr, Tc, Ru, Os, Re, C, Pd, Pt, Rh, Ir, Cd, or W

First Aggregation Layer Material

second aggregation layer material

Foundation Second Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Cvd Growth

Step 1

Process details

catalyst:Ni, Co, Fe, or Cu

precursors:carbon-containing source gas

description:Chemical vapor deposition (CVD) process used for depositing carbon on the catalyst layer and growing graphene. The convex (protruding) area of the catalyst layer functions as a growth starting point. Monolayer graphenes grow from the side surface of the convex area and laminate parallel to the side surface, forming a continuous graphene layer without break.

Materials:

Why these are connected

Related documents with shared materials, methods, properties, or citations.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Matter42 Literature