SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER

Junjing Bao

Patent

Atlas literature

Patent

US 9,324,635

SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER

Junjing Bao

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

1 independent · 9 dependent

1
Independentgraphene-based barrier metal layerCuCucapping layersemiconductor interconnect structure
(Cu rr ently Amended) An interconnect structure comprising: at least one opening in a dielectric layer, the at least one opening including at least a bottom and one or more adjacent sidewalls; a graphene-based ba rr ier metal layer disposed directly on the at least one opening in the dielectric layer, wherein the graphene-based barrier metal layer is disposed directly on the one or more adjacent sidewalls of the dielectric layer and the graphene-based barrier metal layer is disposed directly on the bottom of the dielectric layer a seed layer disposed on the graphene-based barrier metal layer; an electroplated copper layer disposed on the seed layer; a planarized surface, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed; and a capping layer disposed on the planarized surface.
1. 2
  Dependent← claim 1semiconductor interconnect structure
  The interconnect structure of claim 1, wherein the at least one opening further comprises a trench area, a trench area with at least one via hole, or a combination thereof.
2. 3
  Dependent← claim 1graphene-based barrier metal layersemiconductor interconnect structure
  (Cu rr ently Amended) The interconnect structure of claim 1, wherein: the graphene-based barrier metal layer is formed utilizing electrostatic deposition at a temperature ranging from about 15 ° C to about 25 °C; the graphene-based barrier metal layer comprises a single atomic layer of sp2-bonded carbon atoms densely packed into a hexagonal crystal lattice; and the graphene-based barrier metal layer has a thickness of about O.15 nm. Page 2 of 7 Docket No. F I S₉₂₀₁₁₀₁₇₇US₂ Application No. 14/525,886
3. 4
  Dependent← claim 1graphene-based barrier metal layersemiconductor interconnect structure
  (Cu rr ently Amended) The interconnect structure of claim 1, wherein: the graphene-based barrier metal layer is formed utilizing electrostatic deposition at a temperature ranging from about 15 ° C to about 25 °C; the graphene-based barrier metal layer is multi-layered and comprises more than one single atomic layer of sp 2 -bonded carbon atoms densely packed into a hexagonal crystal lattice; and the graphene-based barrier metal layer has a thickness ranging from about 0.3nm to about 0.9nm.
4. 5
  Dependent← claim 1graphene-based barrier metal layertantalum and graphene alloytantalum nitride and graphene alloysemiconductor interconnect structure
  (Cu rr ently Amended) The interconnect structure of claim 1, wherein: the graphene-based barrier metal layer is formed utilizing chemical vapor deposition (CVD) at a temperature ranging from about 25 ° C to about 400 °C; the graphene-based barrier metal layer is a metal alloy comprising tantalum and graphene, or tantalum nitride and graphene; and the graphene-based barrier metal layer has a thickness ranging from about O.15 nm to about 0.9nm.
5. 6
  Dependent← claim 1Cusemiconductor interconnect structure
  The interconnect structure of claim 1, wherein: the seed layer is formed utilizing physical vapor deposition (PVD) or chemical vapor deposition (CVD); and the seed layer comprises pure copper. Page 3 of 7 Docket No. F I S₉₂₀₁₁₀₁₇₇US₂ Application No. 14/525,886
6. 7
  Dependent← claim 1Cucopper alloy with impurities (Mn, Al, Sn)semiconductor interconnect structure
  The interconnect structure of claim 1, wherein: the seed layer is formed utilizing physical vapor deposition (PVD) or chemical vapor deposition (CVD); the seed layer comprises a copper alloy having impurities; and the impurities include manganese, aluminum, tin, or a combination thereof.
7. 8
  Dependent← claim 1Cusemiconductor interconnect structure
  The interconnect structure of claim 1, wherein the electroplated copper layer is annealed at a temperature ranging from about 50 ° C to about 350 ° C to enhance grain growth of copper within the interconnect structure.
8. 10
  Dependent← claim 1capping layersemiconductor interconnect structure
  The interconnect structure of claim 1, wherein: the capping layer is formed utilizing chemical vapor deposition (CVD) and at a temperature ranging from about 350 ° C to about 400 ° C; and the capping layer is a dielectric capping layer. Page 4 of 7

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor interconnect structure

capping layercapping layer

Cuconductor fill

Cuseed layer

graphene-based barrier metal layerbarrier metal

dielectric layerdielectric

Materials

Materials described outside the worked examples.

graphene-based barrier metal layer

Barrier Metal Layer

seed layer (copper)

Seed Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Electrostatic Deposition

Step 1

Temperature

15, 25°C

Process details

layer type:single atomic layer graphene

thickness nm:0.15

Materials:

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
graphene-based barrier metal layer thickness (single layer)	0.15 nm	graphene-based barrier metal layer
graphene-based barrier metal layer thickness (multi-layer) range	0.3–0.9 nm

Why these are connected

Related documents with shared materials, methods, properties, or citations.

SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER | Matter42 Literature