Wafer Fabrication: providing a finished wafer (GaN-on-Si wafer) comprising a 30 plurality of GaN-on-Si die, comprising on-chip metal defining source, drain and gate contact areas of each die (first level of interconnect).

Post-processing of the GaN-on-Si wafer: providing and patterning a copper redistribution layer (Cu RDL) defining large area source, drain and gate contact areas (second level of interconnect) for each die, and dicing of the wafer to provide 35 individual GaN-on-Si chips. 5 3. Packaging of the singulated GaN-on-Si chips: Assembly of packaging components comprising a dielectric package body and overlying and underlying metal foil layers, and interconnection of internal source, drain and gate contract areas to back-side external source, drain and gate pads (third level of interconnect) and die attach to the thermal pad. [0067] Wafer Fabrication: [0068] Fig.5A illustrates schematically a top view of one GaN-on-Si chip 102 after completion of conventional chip fabrication steps to provide an on-chip metal layer 110 15 which defines metal tracks for the source contact area 112, drain contact area 114, and gate contact areas 116 of the GaN-on-Si chip. In this embodiment, the source and drain metal tracks 112 and 114 comprise interdigitated source and drain fingers to form a large gate width GaN transistor. 20 [0069] Wafer post-processing: [0070] Fig. 5B shows schematically a top view of the GaN-on-Si die of Fig. 5A after providing thereon a second level of interconnect comprising the Cu RDL 120. During post-processing of the Ga-N chip, a dielectric layer of polyimide 118 is applied to the chip 25 and patterned to open contact openings to the underlying on-chip metal layer 110, and the Cu RDL is applied and patterned to define the large source contact area 127, drain contact area 124 and gate contact areas 124, as shown schematically in Fig. 5B. Post-processing may also include other conventional post-processing steps, such as, back-side thinning of the wafer and application of a back-side metal layer for die attach. The 30 wafer is then diced to provide individual GaN-on-Si chips 102, comprising on-chip metal 110 and overlying Cu RDL 120. This structure is shown schematically in cross-section in Fig. 5 C, through line C-C of Fig. 5B. Thus, figure 5C shows in cross-section the GaN-on-Si chip 102, comprising the silicon substrate 104 and overlying G aN layers 104, the on-chip metal layer 110, the 35 polyimide layer 118, and Cu RDL 120. 5 [0071] Packaging: [0072] Each individual GaN-on-Si chip is embedded in one or more layers of package dielectric 127, i.e. high temp fiberglass (FR₄) as illustrated schematically in the cross- sectional view of Fig. 5C. The dielectric layer material 127 extends over and under the 10 GaN-on-Si chip to completely embed it. The package dielectric layers 127, with the embedded GaN-on-Si chip(s) 102 are then sandwiched between overlying and underlying package metal layers 130 and 140, each comprising a thick copper foil layer which extends over the front and back surfaces of the package body. 15 [0073] Subsequently, the overlying (front-side) copper foil layer 130 is patterned to define the large area contact areas 132, 134 and 136, for the source, drain and gate respectively, as shown in Fig. 2A. The source and drain contact areas 132 and 134 are seen in the cross section of Fig. 5 C. The underlying (back-side) copper foil layer 140 is patterned to define the thermal pad 150 and external contact pads 142, 144, 146, 148 for the source, drain, gate 20 and source sense respectively, as shown in Fig. 2B. The source and drain pads 142 and 144, and thermal pad 150 are seen in the cross-section of Fig. 5C. [0074] Interconnection of the source, drain and gate contact areas of the Cu RDL on the GaN-on-Si chip and the 25 respective source drain and gate contact areas of package interconnect comprising copper foil layer 130 is accomplished by forming copper pillars and/or posts as described above with reference to Fig 1, and Figs 2A to 2D. [0075] In one embodiment, these interconnect pillars and posts, are provided by opening sets of vias through contact areas defined by the 30 overlying and underlying copper foil layers, to respective contact areas and then plating copper therein, to form conductive copper pillars and/or posts. For small copper posts 128, interconnecting the overlying copper foil layer 130 to respective contact areas of the Cu RDL layer 120, small dimension vias extending through the copper foil layer 130 to the Cu RDL are formed by laser drilling. For copper pillars 190, larger through hole vias, extending from copper layer 130 through 35 the dielectric to copper layer 140, are formed by conventional drilling techniques. For thermal copper posts 152, which also provide electrical contact with the back-side of the 20 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 chip 102, another set of small vias is opened through the underlying copper foil layer 140 through to the back-side metal of the chip 102. The vias are filled by copper plating to form the copper pillars and posts, 128, 152 and 190. [0076] Typically, for volume production, batch processing is used in which large sheets 10 of dielectric layers 127 are patterned for embedding multiple GaN-on Si chips 102. After applying and patterning the copper foil layers 130 and 140, the interconnections comprising the copper pillars and posts are fo rm ed as described above using an appropriate drilling and plating process. The sheet is then cut to separate the individual packaging assemblies each comprising an individual embedded GaN-on-Si chip. [0077] As is conventional, the packaging assembly may be finished with a covering or encapsulation layer (not shown). This covering protects the contact areas on the front-side of the package and provides an area for labelling. The external contact pads for the source, drain, gate and source sense (142, 144, 146 and 148 in Fig. 2 B), and the thermal pad (150 20 in Fig. 2 B) are left exposed on the back-side of the package. Thus the package may be mounted on an underlying thermal substrate, e.g. on a printed circuit board providing thermal vias for heat dissipation from the external thermal pad of the package, and corresponding source, drain, gate and source sense contact areas for electrical connections. 25 [0078] Alternative embodiments [0079] As will be appreciated, while specific embodiments have been described above, modifications or variants of these embodiments may be provided. In particular, as shown in the embodiments described above, alternative arrangements may be used for 30 interconnecting the conductive elements of the second level interconnect and the third level interconnect, using various arrangements of conductive layers and conductive posts or pillars. The packages may be assembled using other process sequences. For example, openings for the interconnect pillars and posts may be pre-drilled through the dielectric layers before assembly to accommodate copper posts already in place, the dielectric layers 35 may be formed around the copper posts, or, as described above, the chip is embedded in the dielectric layers of the package and sandwiched between copper foil layers of the 21 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 package, before forming openings or via s and plating of copper areas, posts or pillars forming the interconnections. [0080] In some embodiments, more than one chip may be embedded in a single package assembly, for example a GaN power transistor chip may be co-packaged with one or more other GaN power transistors. The GaN power transistor chip may comprise integrated driver circuitry, and/or it may be co-packaged with another chip, e.g. a MOSFET comprising driver circuitry. [0081] The conductive layers, posts, and pillars preferably comprise copper or copper 15 alloy. Alternatively, they may comprise other suitable metals and metal alloys, or composites, which are typically used for semiconductor packaging components, providing they have sufficient current capability and thermal conductivity, and an appropriate coefficient of thermal expansion (C TE). 20 [0082] In embodiments where the back-side of the GaN-on-Si die is directly attached to the thermal pad, sintered silver is preferred as a low inductance, and thermally conductive die-attach material, to provide both an electrical connection and thermal connection of the back-side of the GaN die and the thermal pad. Alternatives to sintered silver comprise, for example, silver impregnated epoxy, lead free solder, or similar die-attach materials. [0083] In embodiments where an intervening layer of interconnect material is required to make electrical connections between metal posts or pillars and overlying or underlying metal layers, interconnect materials are selected that are excellent electrical conductors, capable of withstanding power cycling, and where possible lead-free. Sintered silver 30 provides excellent electrical conductivity and is also excellent thermal conductor. In some embodiments, solder tipped copper pillars may be preferred. For any soldered connections, lead-free solder is preferred. [0084] Fabrication and performance considerations 35 22 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 [0085] Embedded packaging assemblies for lateral GaN power devices and systems according to embodiments disclosed herein have low inductance, and can carry an increased current relative to conventional wirebonded packages. The package can be fabricated at reasonable cost and with a lower profile (i.e. made thinner) than conventional wirebonded arrangements. [0086] In preferred embodiments, the second level of interconnect comprises thick copper RDL to provide large area, low inductance on-chip source and drain contacts for higher current handling capability. Structures according to embodiments of the invention also provide thermal contact between the back-side of the lateral GaN-on-Si die and a thermal 15 substrate, which reduces thermal impedance (i.e. provides shorter thermal path) and improves device performance. [0087] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example 20 only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims. Claims What is claimed is:

Wafer Fabrication: providing a finished wafer (GaN-on-Si wafer) comprising a 30 plurality of GaN-on-Si die, comprising on-chip metal defining source, drain and gate contact areas of each die (first level of interconnect).

Post-processing of the GaN-on-Si wafer: providing and patterning a copper redistribution layer (Cu RDL) defining large area source, drain and gate contact areas (second level of interconnect) for each die, and dicing of the wafer to provide 35 individual GaN-on-Si chips. 5 3. Packaging of the singulated GaN-on-Si chips: Assembly of packaging components comprising a dielectric package body and overlying and underlying metal foil layers, and interconnection of internal source, drain and gate contract areas to back-side external source, drain and gate pads (third level of interconnect) and die attach to the thermal pad. [0067] Wafer Fabrication: [0068] Fig.5A illustrates schematically a top view of one GaN-on-Si chip 102 after completion of conventional chip fabrication steps to provide an on-chip metal layer 110 15 which defines metal tracks for the source contact area 112, drain contact area 114, and gate contact areas 116 of the GaN-on-Si chip. In this embodiment, the source and drain metal tracks 112 and 114 comprise interdigitated source and drain fingers to form a large gate width GaN transistor. 20 [0069] Wafer post-processing: [0070] Fig. 5B shows schematically a top view of the GaN-on-Si die of Fig. 5A after providing thereon a second level of interconnect comprising the Cu RDL 120. During post-processing of the Ga-N chip, a dielectric layer of polyimide 118 is applied to the chip 25 and patterned to open contact openings to the underlying on-chip metal layer 110, and the Cu RDL is applied and patterned to define the large source contact area 127, drain contact area 124 and gate contact areas 124, as shown schematically in Fig. 5B. Post-processing may also include other conventional post-processing steps, such as, back-side thinning of the wafer and application of a back-side metal layer for die attach. The 30 wafer is then diced to provide individual GaN-on-Si chips 102, comprising on-chip metal 110 and overlying Cu RDL 120. This structure is shown schematically in cross-section in Fig. 5 C, through line C-C of Fig. 5B. Thus, figure 5C shows in cross-section the GaN-on-Si chip 102, comprising the silicon substrate 104 and overlying G aN layers 104, the on-chip metal layer 110, the 35 polyimide layer 118, and Cu RDL 120. 5 [0071] Packaging: [0072] Each individual GaN-on-Si chip is embedded in one or more layers of package dielectric 127, i.e. high temp fiberglass (FR₄) as illustrated schematically in the cross- sectional view of Fig. 5C. The dielectric layer material 127 extends over and under the 10 GaN-on-Si chip to completely embed it. The package dielectric layers 127, with the embedded GaN-on-Si chip(s) 102 are then sandwiched between overlying and underlying package metal layers 130 and 140, each comprising a thick copper foil layer which extends over the front and back surfaces of the package body. 15 [0073] Subsequently, the overlying (front-side) copper foil layer 130 is patterned to define the large area contact areas 132, 134 and 136, for the source, drain and gate respectively, as shown in Fig. 2A. The source and drain contact areas 132 and 134 are seen in the cross section of Fig. 5 C. The underlying (back-side) copper foil layer 140 is patterned to define the thermal pad 150 and external contact pads 142, 144, 146, 148 for the source, drain, gate 20 and source sense respectively, as shown in Fig. 2B. The source and drain pads 142 and 144, and thermal pad 150 are seen in the cross-section of Fig. 5C. [0074] Interconnection of the source, drain and gate contact areas of the Cu RDL on the GaN-on-Si chip and the 25 respective source drain and gate contact areas of package interconnect comprising copper foil layer 130 is accomplished by forming copper pillars and/or posts as described above with reference to Fig 1, and Figs 2A to 2D. [0075] In one embodiment, these interconnect pillars and posts, are provided by opening sets of vias through contact areas defined by the 30 overlying and underlying copper foil layers, to respective contact areas and then plating copper therein, to form conductive copper pillars and/or posts. For small copper posts 128, interconnecting the overlying copper foil layer 130 to respective contact areas of the Cu RDL layer 120, small dimension vias extending through the copper foil layer 130 to the Cu RDL are formed by laser drilling. For copper pillars 190, larger through hole vias, extending from copper layer 130 through 35 the dielectric to copper layer 140, are formed by conventional drilling techniques. For thermal copper posts 152, which also provide electrical contact with the back-side of the 20 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 chip 102, another set of small vias is opened through the underlying copper foil layer 140 through to the back-side metal of the chip 102. The vias are filled by copper plating to form the copper pillars and posts, 128, 152 and 190. [0076] Typically, for volume production, batch processing is used in which large sheets 10 of dielectric layers 127 are patterned for embedding multiple GaN-on Si chips 102. After applying and patterning the copper foil layers 130 and 140, the interconnections comprising the copper pillars and posts are fo rm ed as described above using an appropriate drilling and plating process. The sheet is then cut to separate the individual packaging assemblies each comprising an individual embedded GaN-on-Si chip. [0077] As is conventional, the packaging assembly may be finished with a covering or encapsulation layer (not shown). This covering protects the contact areas on the front-side of the package and provides an area for labelling. The external contact pads for the source, drain, gate and source sense (142, 144, 146 and 148 in Fig. 2 B), and the thermal pad (150 20 in Fig. 2 B) are left exposed on the back-side of the package. Thus the package may be mounted on an underlying thermal substrate, e.g. on a printed circuit board providing thermal vias for heat dissipation from the external thermal pad of the package, and corresponding source, drain, gate and source sense contact areas for electrical connections. 25 [0078] Alternative embodiments [0079] As will be appreciated, while specific embodiments have been described above, modifications or variants of these embodiments may be provided. In particular, as shown in the embodiments described above, alternative arrangements may be used for 30 interconnecting the conductive elements of the second level interconnect and the third level interconnect, using various arrangements of conductive layers and conductive posts or pillars. The packages may be assembled using other process sequences. For example, openings for the interconnect pillars and posts may be pre-drilled through the dielectric layers before assembly to accommodate copper posts already in place, the dielectric layers 35 may be formed around the copper posts, or, as described above, the chip is embedded in the dielectric layers of the package and sandwiched between copper foil layers of the 21 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 package, before forming openings or via s and plating of copper areas, posts or pillars forming the interconnections. [0080] In some embodiments, more than one chip may be embedded in a single package assembly, for example a GaN power transistor chip may be co-packaged with one or more other GaN power transistors. The GaN power transistor chip may comprise integrated driver circuitry, and/or it may be co-packaged with another chip, e.g. a MOSFET comprising driver circuitry. [0081] The conductive layers, posts, and pillars preferably comprise copper or copper 15 alloy. Alternatively, they may comprise other suitable metals and metal alloys, or composites, which are typically used for semiconductor packaging components, providing they have sufficient current capability and thermal conductivity, and an appropriate coefficient of thermal expansion (C TE). 20 [0082] In embodiments where the back-side of the GaN-on-Si die is directly attached to the thermal pad, sintered silver is preferred as a low inductance, and thermally conductive die-attach material, to provide both an electrical connection and thermal connection of the back-side of the GaN die and the thermal pad. Alternatives to sintered silver comprise, for example, silver impregnated epoxy, lead free solder, or similar die-attach materials. [0083] In embodiments where an intervening layer of interconnect material is required to make electrical connections between metal posts or pillars and overlying or underlying metal layers, interconnect materials are selected that are excellent electrical conductors, capable of withstanding power cycling, and where possible lead-free. Sintered silver 30 provides excellent electrical conductivity and is also excellent thermal conductor. In some embodiments, solder tipped copper pillars may be preferred. For any soldered connections, lead-free solder is preferred. [0084] Fabrication and performance considerations 35 22 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 [0085] Embedded packaging assemblies for lateral GaN power devices and systems according to embodiments disclosed herein have low inductance, and can carry an increased current relative to conventional wirebonded packages. The package can be fabricated at reasonable cost and with a lower profile (i.e. made thinner) than conventional wirebonded arrangements. [0086] In preferred embodiments, the second level of interconnect comprises thick copper RDL to provide large area, low inductance on-chip source and drain contacts for higher current handling capability. Structures according to embodiments of the invention also provide thermal contact between the back-side of the lateral GaN-on-Si die and a thermal 15 substrate, which reduces thermal impedance (i.e. provides shorter thermal path) and improves device performance. [0087] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example 20 only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims. Claims What is claimed is:

Wafer Fabrication: providing a finished wafer (GaN-on-Si wafer) comprising a 30 plurality of GaN-on-Si die, comprising on-chip metal defining source, drain and gate contact areas of each die (first level of interconnect).

Post-processing of the GaN-on-Si wafer: providing and patterning a copper redistribution layer (Cu RDL) defining large area source, drain and gate contact areas (second level of interconnect) for each die, and dicing of the wafer to provide 35 individual GaN-on-Si chips. 5 3. Packaging of the singulated GaN-on-Si chips: Assembly of packaging components comprising a dielectric package body and overlying and underlying metal foil layers, and interconnection of internal source, drain and gate contract areas to back-side external source, drain and gate pads (third level of interconnect) and die attach to the thermal pad. [0067] Wafer Fabrication: [0068] Fig.5A illustrates schematically a top view of one GaN-on-Si chip 102 after completion of conventional chip fabrication steps to provide an on-chip metal layer 110 15 which defines metal tracks for the source contact area 112, drain contact area 114, and gate contact areas 116 of the GaN-on-Si chip. In this embodiment, the source and drain metal tracks 112 and 114 comprise interdigitated source and drain fingers to form a large gate width GaN transistor. 20 [0069] Wafer post-processing: [0070] Fig. 5B shows schematically a top view of the GaN-on-Si die of Fig. 5A after providing thereon a second level of interconnect comprising the Cu RDL 120. During post-processing of the Ga-N chip, a dielectric layer of polyimide 118 is applied to the chip 25 and patterned to open contact openings to the underlying on-chip metal layer 110, and the Cu RDL is applied and patterned to define the large source contact area 127, drain contact area 124 and gate contact areas 124, as shown schematically in Fig. 5B. Post-processing may also include other conventional post-processing steps, such as, back-side thinning of the wafer and application of a back-side metal layer for die attach. The 30 wafer is then diced to provide individual GaN-on-Si chips 102, comprising on-chip metal 110 and overlying Cu RDL 120. This structure is shown schematically in cross-section in Fig. 5 C, through line C-C of Fig. 5B. Thus, figure 5C shows in cross-section the GaN-on-Si chip 102, comprising the silicon substrate 104 and overlying G aN layers 104, the on-chip metal layer 110, the 35 polyimide layer 118, and Cu RDL 120. 5 [0071] Packaging: [0072] Each individual GaN-on-Si chip is embedded in one or more layers of package dielectric 127, i.e. high temp fiberglass (FR₄) as illustrated schematically in the cross- sectional view of Fig. 5C. The dielectric layer material 127 extends over and under the 10 GaN-on-Si chip to completely embed it. The package dielectric layers 127, with the embedded GaN-on-Si chip(s) 102 are then sandwiched between overlying and underlying package metal layers 130 and 140, each comprising a thick copper foil layer which extends over the front and back surfaces of the package body. 15 [0073] Subsequently, the overlying (front-side) copper foil layer 130 is patterned to define the large area contact areas 132, 134 and 136, for the source, drain and gate respectively, as shown in Fig. 2A. The source and drain contact areas 132 and 134 are seen in the cross section of Fig. 5 C. The underlying (back-side) copper foil layer 140 is patterned to define the thermal pad 150 and external contact pads 142, 144, 146, 148 for the source, drain, gate 20 and source sense respectively, as shown in Fig. 2B. The source and drain pads 142 and 144, and thermal pad 150 are seen in the cross-section of Fig. 5C. [0074] Interconnection of the source, drain and gate contact areas of the Cu RDL on the GaN-on-Si chip and the 25 respective source drain and gate contact areas of package interconnect comprising copper foil layer 130 is accomplished by forming copper pillars and/or posts as described above with reference to Fig 1, and Figs 2A to 2D. [0075] In one embodiment, these interconnect pillars and posts, are provided by opening sets of vias through contact areas defined by the 30 overlying and underlying copper foil layers, to respective contact areas and then plating copper therein, to form conductive copper pillars and/or posts. For small copper posts 128, interconnecting the overlying copper foil layer 130 to respective contact areas of the Cu RDL layer 120, small dimension vias extending through the copper foil layer 130 to the Cu RDL are formed by laser drilling. For copper pillars 190, larger through hole vias, extending from copper layer 130 through 35 the dielectric to copper layer 140, are formed by conventional drilling techniques. For thermal copper posts 152, which also provide electrical contact with the back-side of the 20 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 chip 102, another set of small vias is opened through the underlying copper foil layer 140 through to the back-side metal of the chip 102. The vias are filled by copper plating to form the copper pillars and posts, 128, 152 and 190. [0076] Typically, for volume production, batch processing is used in which large sheets 10 of dielectric layers 127 are patterned for embedding multiple GaN-on Si chips 102. After applying and patterning the copper foil layers 130 and 140, the interconnections comprising the copper pillars and posts are fo rm ed as described above using an appropriate drilling and plating process. The sheet is then cut to separate the individual packaging assemblies each comprising an individual embedded GaN-on-Si chip. [0077] As is conventional, the packaging assembly may be finished with a covering or encapsulation layer (not shown). This covering protects the contact areas on the front-side of the package and provides an area for labelling. The external contact pads for the source, drain, gate and source sense (142, 144, 146 and 148 in Fig. 2 B), and the thermal pad (150 20 in Fig. 2 B) are left exposed on the back-side of the package. Thus the package may be mounted on an underlying thermal substrate, e.g. on a printed circuit board providing thermal vias for heat dissipation from the external thermal pad of the package, and corresponding source, drain, gate and source sense contact areas for electrical connections. 25 [0078] Alternative embodiments [0079] As will be appreciated, while specific embodiments have been described above, modifications or variants of these embodiments may be provided. In particular, as shown in the embodiments described above, alternative arrangements may be used for 30 interconnecting the conductive elements of the second level interconnect and the third level interconnect, using various arrangements of conductive layers and conductive posts or pillars. The packages may be assembled using other process sequences. For example, openings for the interconnect pillars and posts may be pre-drilled through the dielectric layers before assembly to accommodate copper posts already in place, the dielectric layers 35 may be formed around the copper posts, or, as described above, the chip is embedded in the dielectric layers of the package and sandwiched between copper foil layers of the 21 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 package, before forming openings or via s and plating of copper areas, posts or pillars forming the interconnections. [0080] In some embodiments, more than one chip may be embedded in a single package assembly, for example a GaN power transistor chip may be co-packaged with one or more other GaN power transistors. The GaN power transistor chip may comprise integrated driver circuitry, and/or it may be co-packaged with another chip, e.g. a MOSFET comprising driver circuitry. [0081] The conductive layers, posts, and pillars preferably comprise copper or copper 15 alloy. Alternatively, they may comprise other suitable metals and metal alloys, or composites, which are typically used for semiconductor packaging components, providing they have sufficient current capability and thermal conductivity, and an appropriate coefficient of thermal expansion (C TE). 20 [0082] In embodiments where the back-side of the GaN-on-Si die is directly attached to the thermal pad, sintered silver is preferred as a low inductance, and thermally conductive die-attach material, to provide both an electrical connection and thermal connection of the back-side of the GaN die and the thermal pad. Alternatives to sintered silver comprise, for example, silver impregnated epoxy, lead free solder, or similar die-attach materials. [0083] In embodiments where an intervening layer of interconnect material is required to make electrical connections between metal posts or pillars and overlying or underlying metal layers, interconnect materials are selected that are excellent electrical conductors, capable of withstanding power cycling, and where possible lead-free. Sintered silver 30 provides excellent electrical conductivity and is also excellent thermal conductor. In some embodiments, solder tipped copper pillars may be preferred. For any soldered connections, lead-free solder is preferred. [0084] Fabrication and performance considerations 35 22 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 [0085] Embedded packaging assemblies for lateral GaN power devices and systems according to embodiments disclosed herein have low inductance, and can carry an increased current relative to conventional wirebonded packages. The package can be fabricated at reasonable cost and with a lower profile (i.e. made thinner) than conventional wirebonded arrangements. [0086] In preferred embodiments, the second level of interconnect comprises thick copper RDL to provide large area, low inductance on-chip source and drain contacts for higher current handling capability. Structures according to embodiments of the invention also provide thermal contact between the back-side of the lateral GaN-on-Si die and a thermal 15 substrate, which reduces thermal impedance (i.e. provides shorter thermal path) and improves device performance. [0087] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example 20 only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims. Claims What is claimed is:

Wafer Fabrication: providing a finished wafer (GaN-on-Si wafer) comprising a 30 plurality of GaN-on-Si die, comprising on-chip metal defining source, drain and gate contact areas of each die (first level of interconnect).

Post-processing of the GaN-on-Si wafer: providing and patterning a copper redistribution layer (Cu RDL) defining large area source, drain and gate contact areas (second level of interconnect) for each die, and dicing of the wafer to provide 35 individual GaN-on-Si chips. 5 3. Packaging of the singulated GaN-on-Si chips: Assembly of packaging components comprising a dielectric package body and overlying and underlying metal foil layers, and interconnection of internal source, drain and gate contract areas to back-side external source, drain and gate pads (third level of interconnect) and die attach to the thermal pad. [0067] Wafer Fabrication: [0068] Fig.5A illustrates schematically a top view of one GaN-on-Si chip 102 after completion of conventional chip fabrication steps to provide an on-chip metal layer 110 15 which defines metal tracks for the source contact area 112, drain contact area 114, and gate contact areas 116 of the GaN-on-Si chip. In this embodiment, the source and drain metal tracks 112 and 114 comprise interdigitated source and drain fingers to form a large gate width GaN transistor. 20 [0069] Wafer post-processing: [0070] Fig. 5B shows schematically a top view of the GaN-on-Si die of Fig. 5A after providing thereon a second level of interconnect comprising the Cu RDL 120. During post-processing of the Ga-N chip, a dielectric layer of polyimide 118 is applied to the chip 25 and patterned to open contact openings to the underlying on-chip metal layer 110, and the Cu RDL is applied and patterned to define the large source contact area 127, drain contact area 124 and gate contact areas 124, as shown schematically in Fig. 5B. Post-processing may also include other conventional post-processing steps, such as, back-side thinning of the wafer and application of a back-side metal layer for die attach. The 30 wafer is then diced to provide individual GaN-on-Si chips 102, comprising on-chip metal 110 and overlying Cu RDL 120. This structure is shown schematically in cross-section in Fig. 5 C, through line C-C of Fig. 5B. Thus, figure 5C shows in cross-section the GaN-on-Si chip 102, comprising the silicon substrate 104 and overlying G aN layers 104, the on-chip metal layer 110, the 35 polyimide layer 118, and Cu RDL 120. 5 [0071] Packaging: [0072] Each individual GaN-on-Si chip is embedded in one or more layers of package dielectric 127, i.e. high temp fiberglass (FR₄) as illustrated schematically in the cross- sectional view of Fig. 5C. The dielectric layer material 127 extends over and under the 10 GaN-on-Si chip to completely embed it. The package dielectric layers 127, with the embedded GaN-on-Si chip(s) 102 are then sandwiched between overlying and underlying package metal layers 130 and 140, each comprising a thick copper foil layer which extends over the front and back surfaces of the package body. 15 [0073] Subsequently, the overlying (front-side) copper foil layer 130 is patterned to define the large area contact areas 132, 134 and 136, for the source, drain and gate respectively, as shown in Fig. 2A. The source and drain contact areas 132 and 134 are seen in the cross section of Fig. 5 C. The underlying (back-side) copper foil layer 140 is patterned to define the thermal pad 150 and external contact pads 142, 144, 146, 148 for the source, drain, gate 20 and source sense respectively, as shown in Fig. 2B. The source and drain pads 142 and 144, and thermal pad 150 are seen in the cross-section of Fig. 5C. [0074] Interconnection of the source, drain and gate contact areas of the Cu RDL on the GaN-on-Si chip and the 25 respective source drain and gate contact areas of package interconnect comprising copper foil layer 130 is accomplished by forming copper pillars and/or posts as described above with reference to Fig 1, and Figs 2A to 2D. [0075] In one embodiment, these interconnect pillars and posts, are provided by opening sets of vias through contact areas defined by the 30 overlying and underlying copper foil layers, to respective contact areas and then plating copper therein, to form conductive copper pillars and/or posts. For small copper posts 128, interconnecting the overlying copper foil layer 130 to respective contact areas of the Cu RDL layer 120, small dimension vias extending through the copper foil layer 130 to the Cu RDL are formed by laser drilling. For copper pillars 190, larger through hole vias, extending from copper layer 130 through 35 the dielectric to copper layer 140, are formed by conventional drilling techniques. For thermal copper posts 152, which also provide electrical contact with the back-side of the 20 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 chip 102, another set of small vias is opened through the underlying copper foil layer 140 through to the back-side metal of the chip 102. The vias are filled by copper plating to form the copper pillars and posts, 128, 152 and 190. [0076] Typically, for volume production, batch processing is used in which large sheets 10 of dielectric layers 127 are patterned for embedding multiple GaN-on Si chips 102. After applying and patterning the copper foil layers 130 and 140, the interconnections comprising the copper pillars and posts are fo rm ed as described above using an appropriate drilling and plating process. The sheet is then cut to separate the individual packaging assemblies each comprising an individual embedded GaN-on-Si chip. [0077] As is conventional, the packaging assembly may be finished with a covering or encapsulation layer (not shown). This covering protects the contact areas on the front-side of the package and provides an area for labelling. The external contact pads for the source, drain, gate and source sense (142, 144, 146 and 148 in Fig. 2 B), and the thermal pad (150 20 in Fig. 2 B) are left exposed on the back-side of the package. Thus the package may be mounted on an underlying thermal substrate, e.g. on a printed circuit board providing thermal vias for heat dissipation from the external thermal pad of the package, and corresponding source, drain, gate and source sense contact areas for electrical connections. 25 [0078] Alternative embodiments [0079] As will be appreciated, while specific embodiments have been described above, modifications or variants of these embodiments may be provided. In particular, as shown in the embodiments described above, alternative arrangements may be used for 30 interconnecting the conductive elements of the second level interconnect and the third level interconnect, using various arrangements of conductive layers and conductive posts or pillars. The packages may be assembled using other process sequences. For example, openings for the interconnect pillars and posts may be pre-drilled through the dielectric layers before assembly to accommodate copper posts already in place, the dielectric layers 35 may be formed around the copper posts, or, as described above, the chip is embedded in the dielectric layers of the package and sandwiched between copper foil layers of the 21 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 package, before forming openings or via s and plating of copper areas, posts or pillars forming the interconnections. [0080] In some embodiments, more than one chip may be embedded in a single package assembly, for example a GaN power transistor chip may be co-packaged with one or more other GaN power transistors. The GaN power transistor chip may comprise integrated driver circuitry, and/or it may be co-packaged with another chip, e.g. a MOSFET comprising driver circuitry. [0081] The conductive layers, posts, and pillars preferably comprise copper or copper 15 alloy. Alternatively, they may comprise other suitable metals and metal alloys, or composites, which are typically used for semiconductor packaging components, providing they have sufficient current capability and thermal conductivity, and an appropriate coefficient of thermal expansion (C TE). 20 [0082] In embodiments where the back-side of the GaN-on-Si die is directly attached to the thermal pad, sintered silver is preferred as a low inductance, and thermally conductive die-attach material, to provide both an electrical connection and thermal connection of the back-side of the GaN die and the thermal pad. Alternatives to sintered silver comprise, for example, silver impregnated epoxy, lead free solder, or similar die-attach materials. [0083] In embodiments where an intervening layer of interconnect material is required to make electrical connections between metal posts or pillars and overlying or underlying metal layers, interconnect materials are selected that are excellent electrical conductors, capable of withstanding power cycling, and where possible lead-free. Sintered silver 30 provides excellent electrical conductivity and is also excellent thermal conductor. In some embodiments, solder tipped copper pillars may be preferred. For any soldered connections, lead-free solder is preferred. [0084] Fabrication and performance considerations 35 22 WO 2015/157845 PCT/CA₂₀₁₅/000244 5 [0085] Embedded packaging assemblies for lateral GaN power devices and systems according to embodiments disclosed herein have low inductance, and can carry an increased current relative to conventional wirebonded packages. The package can be fabricated at reasonable cost and with a lower profile (i.e. made thinner) than conventional wirebonded arrangements. [0086] In preferred embodiments, the second level of interconnect comprises thick copper RDL to provide large area, low inductance on-chip source and drain contacts for higher current handling capability. Structures according to embodiments of the invention also provide thermal contact between the back-side of the lateral GaN-on-Si die and a thermal 15 substrate, which reduces thermal impedance (i.e. provides shorter thermal path) and improves device performance. [0087] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example 20 only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims. Claims What is claimed is: