Patent
US 9,029,836CONTROLLED SYNTHESIS OF MONOLITHICALLY-INTEGRATED GRAPHENE STRUCTURE
Jang-Ung Park, SungWoo Nam, Charles M. Lieber
2015-05-12·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,029,836Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a graphene structure 2 c omprising: 3 on a fabrication substrate, forming a pattern of a plurality of 4 gra p hene synthesis catal y st regions, each of the gra p hene synthesis 5 catal y st re g ions in the plurality includin g a different di stmet- graphene 6 c atalyst materia lmater als, and each of the different grap hene catalys t 7 materials havin g a different carbon solubility; and 8 in one graphene synthesis step, ex p osing the different gra p hene 9 c atalyst materials of the p lurality of gra p hene synthesis catal y st regions 10 to a source of carbon, formin g a different number mwber- of graphene 11 layers on the different g raphene catalyst materials in the formed pattern. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises exposure of the graphene catalyst materials to a 3 c arbonaceous gas. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises chemical vapor deposition with methane gas. -2- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.2.1399.207.2247.292.svg 0.283 2.827 Chemistry Black and white Serial No. 13/817,885 1 5. The method of claim 1 wherein the plurality of gra p hene 2 synthesis catal y st regions having different di stinet-graphene catalyst 3 materials com p rise ineludm a ralit f m aterials selected from the 4 g rou p consisting of Co, Cu, Fe, Ge, A l, Ni, Pd, Pt, and Au, alloys thereof, 5 and layered combinations thereof. 1
The method of claim 1 wherein the different plura1ity-ef 2 di se-t-graphene catalyst materials include Iel-des a layered 3 combination of Cu and Ni. 1
The method of claim 1 wherein the different p lrality-ef 2 di et-i-net- graphene catalyst materials include Iemades a layered 3 combination of Cu, Ni, and Co. 1
The method of claim 1 wherein the different pl-a1ity-ef 2 4ie-t- graphene catalyst materials include irelude Cu, Ni, and Co. 1
The method of claim 1 further comprising: 2 applying a layer of handle material on the formed graphene layers; SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.19.281.2223.2039.2313.svg 0.3 5.86 Graph Black and white 4 fabrication substrate from the formed graphene layers; and 5 applying the graphene layers, in the formed pattern, onto an 6 operational substrate. 1 10. The method of claim 1 wherein forming a pattern SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.24.280.2764.2223.2854.svg 0.3 6.477 Graph Black and white -3- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.4.281.420.2213.510.svg 0.3 6.44 Graph Black and white Serial No. 13/817,885 4 graphene electrical connections to the device. 1
The method of claim 1 wherein each in the plurality of 2 graphene synthesis catalyst regions having a different graphene catalyst 3 material has a different catalyst material thickness. 1
A method for fabricating a graphene transistor 2 comprising: 3 on a fabrication substrate, providing at least one graphene catalyst 4 material at a substrate region that is specified for synthesizing a graphene 5 transistor channel, the gra p hene transistor channel catal y st having a first 6 carbon solubility; 7 on the fabrication substrate, providing at least one graphene 8 catalyst material at a substrate region that is specified for synthesizing a 9 graphene transistor source-and at a substrate region that is specified for 10 synthesizing a graphene transistor drain s each of the grap hene transistor 11 source and drain catalyst materials having a carbon solubility that is 12 different than the first carbon solubility; 13 in one graphene synthesis step, forming at least one layer of 14 graphene at the substrate region specified for the graphene transistor 15 channel, and forming at the region specified for the transistor source and 16 the region specified for the transistor drain a plurality of layers of 17 graphene that is greater than the at least one la y er of grap hene of the 18 transistor channel. 1
The method of claim 11 further comprising: 2 applying a layer of a gate dielectric over the formed graphene layers; 3 and 4 forming a graphene transistor gate of a plurality of layers of graphene on the gate dielectric layer. -4- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668757.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 13. The method of claim 11 further comprising: 2 applying a layer of handle material on the formed graphene layers; 3 removing the plurality of catalyst materials and the fabrication 4 substrate from the formed graphene layers; and 5 applying the graphene layers, in a pattern of the transistor channel, 6 transistor source region, and transistor drain region, onto an operational 7 substrate. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 channel comprises Cu and Ni. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 source and a graphene transistor drain comprises Co, Cu, and Ni. 1
The method claim 11 wherein forming at the region 2 specified for the transistor source and the region specified for the 3 transistor drain a plurality of layers of graphene comprises forming at 4 least about 800 l ayers of graphene. 1
The method of claim 11 wherein providing at least one 2 graphene catalyst material at a substrate region comprises providing a 3 graphene transistor channel catalyst region of a first thickness; and 4 wherein providing a graphene catalyst material at a substrate 5 region that is specified for synthesizing a graphene transistor source and 6 providing a graphene catalyst material at a substrate region that is 7 specified for synthesizing a graphene transistor drain comprises providing 8 a graphene transistor source catalyst region and a graphene transistor 9 drain catalyst region each of a second thickness that is greater than the 10 first thickness. -8-
The method of claim 13 wherein the operational 2 substrate comprises a silicon wafer. 1
The method of claim 13 wherein the operational 2 substrate comprises a mechanically flexible, non-rigid material. -5- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 19. The method of claim 13 wherein the operational 2 substrate includes a layer of dielectric material, and further comprising 3 making electrical connection to the operational substrate as a transistor 4 back gate. 1
The method of claim 13 wherein applying the graphene 2 layers, in a pattern of the transistor channel, transistor source, and 3 transistor drain regions, onto an operational substrate comprises applying 4 a plurality of patterns of transistor channel, transistor source, and 5 transistor drain regions onto an operation substrate in an array of 6 graphene transistors. 1
A graphene transistor comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; and 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one layer of grap hene of the transistor channel. 1
The graphene transistor of claim 21 wherein the 2 substrate is electrically conducting and includes a dielectric layer on which 3 the transistor channel, source, and drain are disposed, and is connected as 4 a back gate for the graphene transistor. 1 23. The graphene transistor of claim 21 further comprising: SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.27.280.2854.2125.2944.svg 0.3 6.15 Graph Black and white -6- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668759.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 3 a graphene transistor gate that is disposed on the dielectric layer 4 and comprising a plurality of layers of graphene, and that is connected as a 5 top gate for the graphene transistor. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a flexible, non-rigid material. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a silicon substrate including a layer of silicon dioxide. 1
The graphene transistor of claim 21 wherein the 2 transistor source and transistor drain each comprise a number of layers of 3 graphene that is greater than about 800 layers. 1
The graphene transistor of claim 21 wherein the 2 transistor channel comprises about 1-3 layers of graphene. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a material selected from semitransparent materials 3 and transparent materials. 1
A graphene circuit comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and -7- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668760.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one la y er of gra p hene of the transistor channel; and 9 electrical interconnections to the transistor source and drain, each 10 interconnection comprising a plurality of layers of graphene. 1
The graphene circuit of claim 29 wherein the substrate 2 comprises a silicon substrate including a layer of silicon dioxide. 1
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene circuit
Materials described outside the worked examples.
graphene
graphene synthesis catalyst material
methane gas
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,836Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a graphene structure 2 c omprising: 3 on a fabrication substrate, forming a pattern of a plurality of 4 gra p hene synthesis catal y st regions, each of the gra p hene synthesis 5 catal y st re g ions in the plurality includin g a different di stmet- graphene 6 c atalyst materia lmater als, and each of the different grap hene catalys t 7 materials havin g a different carbon solubility; and 8 in one graphene synthesis step, ex p osing the different gra p hene 9 c atalyst materials of the p lurality of gra p hene synthesis catal y st regions 10 to a source of carbon, formin g a different number mwber- of graphene 11 layers on the different g raphene catalyst materials in the formed pattern. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises exposure of the graphene catalyst materials to a 3 c arbonaceous gas. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises chemical vapor deposition with methane gas. -2- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.2.1399.207.2247.292.svg 0.283 2.827 Chemistry Black and white Serial No. 13/817,885 1 5. The method of claim 1 wherein the plurality of gra p hene 2 synthesis catal y st regions having different di stinet-graphene catalyst 3 materials com p rise ineludm a ralit f m aterials selected from the 4 g rou p consisting of Co, Cu, Fe, Ge, A l, Ni, Pd, Pt, and Au, alloys thereof, 5 and layered combinations thereof. 1
The method of claim 1 wherein the different plura1ity-ef 2 di se-t-graphene catalyst materials include Iel-des a layered 3 combination of Cu and Ni. 1
The method of claim 1 wherein the different p lrality-ef 2 di et-i-net- graphene catalyst materials include Iemades a layered 3 combination of Cu, Ni, and Co. 1
The method of claim 1 wherein the different pl-a1ity-ef 2 4ie-t- graphene catalyst materials include irelude Cu, Ni, and Co. 1
The method of claim 1 further comprising: 2 applying a layer of handle material on the formed graphene layers; SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.19.281.2223.2039.2313.svg 0.3 5.86 Graph Black and white 4 fabrication substrate from the formed graphene layers; and 5 applying the graphene layers, in the formed pattern, onto an 6 operational substrate. 1 10. The method of claim 1 wherein forming a pattern SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.24.280.2764.2223.2854.svg 0.3 6.477 Graph Black and white -3- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.4.281.420.2213.510.svg 0.3 6.44 Graph Black and white Serial No. 13/817,885 4 graphene electrical connections to the device. 1
The method of claim 1 wherein each in the plurality of 2 graphene synthesis catalyst regions having a different graphene catalyst 3 material has a different catalyst material thickness. 1
A method for fabricating a graphene transistor 2 comprising: 3 on a fabrication substrate, providing at least one graphene catalyst 4 material at a substrate region that is specified for synthesizing a graphene 5 transistor channel, the gra p hene transistor channel catal y st having a first 6 carbon solubility; 7 on the fabrication substrate, providing at least one graphene 8 catalyst material at a substrate region that is specified for synthesizing a 9 graphene transistor source-and at a substrate region that is specified for 10 synthesizing a graphene transistor drain s each of the grap hene transistor 11 source and drain catalyst materials having a carbon solubility that is 12 different than the first carbon solubility; 13 in one graphene synthesis step, forming at least one layer of 14 graphene at the substrate region specified for the graphene transistor 15 channel, and forming at the region specified for the transistor source and 16 the region specified for the transistor drain a plurality of layers of 17 graphene that is greater than the at least one la y er of grap hene of the 18 transistor channel. 1
The method of claim 11 further comprising: 2 applying a layer of a gate dielectric over the formed graphene layers; 3 and 4 forming a graphene transistor gate of a plurality of layers of graphene on the gate dielectric layer. -4- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668757.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 13. The method of claim 11 further comprising: 2 applying a layer of handle material on the formed graphene layers; 3 removing the plurality of catalyst materials and the fabrication 4 substrate from the formed graphene layers; and 5 applying the graphene layers, in a pattern of the transistor channel, 6 transistor source region, and transistor drain region, onto an operational 7 substrate. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 channel comprises Cu and Ni. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 source and a graphene transistor drain comprises Co, Cu, and Ni. 1
The method claim 11 wherein forming at the region 2 specified for the transistor source and the region specified for the 3 transistor drain a plurality of layers of graphene comprises forming at 4 least about 800 l ayers of graphene. 1
The method of claim 11 wherein providing at least one 2 graphene catalyst material at a substrate region comprises providing a 3 graphene transistor channel catalyst region of a first thickness; and 4 wherein providing a graphene catalyst material at a substrate 5 region that is specified for synthesizing a graphene transistor source and 6 providing a graphene catalyst material at a substrate region that is 7 specified for synthesizing a graphene transistor drain comprises providing 8 a graphene transistor source catalyst region and a graphene transistor 9 drain catalyst region each of a second thickness that is greater than the 10 first thickness. -8-
The method of claim 13 wherein the operational 2 substrate comprises a silicon wafer. 1
The method of claim 13 wherein the operational 2 substrate comprises a mechanically flexible, non-rigid material. -5- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 19. The method of claim 13 wherein the operational 2 substrate includes a layer of dielectric material, and further comprising 3 making electrical connection to the operational substrate as a transistor 4 back gate. 1
The method of claim 13 wherein applying the graphene 2 layers, in a pattern of the transistor channel, transistor source, and 3 transistor drain regions, onto an operational substrate comprises applying 4 a plurality of patterns of transistor channel, transistor source, and 5 transistor drain regions onto an operation substrate in an array of 6 graphene transistors. 1
A graphene transistor comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; and 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one layer of grap hene of the transistor channel. 1
The graphene transistor of claim 21 wherein the 2 substrate is electrically conducting and includes a dielectric layer on which 3 the transistor channel, source, and drain are disposed, and is connected as 4 a back gate for the graphene transistor. 1 23. The graphene transistor of claim 21 further comprising: SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.27.280.2854.2125.2944.svg 0.3 6.15 Graph Black and white -6- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668759.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 3 a graphene transistor gate that is disposed on the dielectric layer 4 and comprising a plurality of layers of graphene, and that is connected as a 5 top gate for the graphene transistor. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a flexible, non-rigid material. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a silicon substrate including a layer of silicon dioxide. 1
The graphene transistor of claim 21 wherein the 2 transistor source and transistor drain each comprise a number of layers of 3 graphene that is greater than about 800 layers. 1
The graphene transistor of claim 21 wherein the 2 transistor channel comprises about 1-3 layers of graphene. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a material selected from semitransparent materials 3 and transparent materials. 1
A graphene circuit comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and -7- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668760.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one la y er of gra p hene of the transistor channel; and 9 electrical interconnections to the transistor source and drain, each 10 interconnection comprising a plurality of layers of graphene. 1
The graphene circuit of claim 29 wherein the substrate 2 comprises a silicon substrate including a layer of silicon dioxide. 1
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene circuit
Materials described outside the worked examples.
graphene
graphene synthesis catalyst material
methane gas
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,836Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a graphene structure 2 c omprising: 3 on a fabrication substrate, forming a pattern of a plurality of 4 gra p hene synthesis catal y st regions, each of the gra p hene synthesis 5 catal y st re g ions in the plurality includin g a different di stmet- graphene 6 c atalyst materia lmater als, and each of the different grap hene catalys t 7 materials havin g a different carbon solubility; and 8 in one graphene synthesis step, ex p osing the different gra p hene 9 c atalyst materials of the p lurality of gra p hene synthesis catal y st regions 10 to a source of carbon, formin g a different number mwber- of graphene 11 layers on the different g raphene catalyst materials in the formed pattern. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises exposure of the graphene catalyst materials to a 3 c arbonaceous gas. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises chemical vapor deposition with methane gas. -2- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.2.1399.207.2247.292.svg 0.283 2.827 Chemistry Black and white Serial No. 13/817,885 1 5. The method of claim 1 wherein the plurality of gra p hene 2 synthesis catal y st regions having different di stinet-graphene catalyst 3 materials com p rise ineludm a ralit f m aterials selected from the 4 g rou p consisting of Co, Cu, Fe, Ge, A l, Ni, Pd, Pt, and Au, alloys thereof, 5 and layered combinations thereof. 1
The method of claim 1 wherein the different plura1ity-ef 2 di se-t-graphene catalyst materials include Iel-des a layered 3 combination of Cu and Ni. 1
The method of claim 1 wherein the different p lrality-ef 2 di et-i-net- graphene catalyst materials include Iemades a layered 3 combination of Cu, Ni, and Co. 1
The method of claim 1 wherein the different pl-a1ity-ef 2 4ie-t- graphene catalyst materials include irelude Cu, Ni, and Co. 1
The method of claim 1 further comprising: 2 applying a layer of handle material on the formed graphene layers; SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.19.281.2223.2039.2313.svg 0.3 5.86 Graph Black and white 4 fabrication substrate from the formed graphene layers; and 5 applying the graphene layers, in the formed pattern, onto an 6 operational substrate. 1 10. The method of claim 1 wherein forming a pattern SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.24.280.2764.2223.2854.svg 0.3 6.477 Graph Black and white -3- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.4.281.420.2213.510.svg 0.3 6.44 Graph Black and white Serial No. 13/817,885 4 graphene electrical connections to the device. 1
The method of claim 1 wherein each in the plurality of 2 graphene synthesis catalyst regions having a different graphene catalyst 3 material has a different catalyst material thickness. 1
A method for fabricating a graphene transistor 2 comprising: 3 on a fabrication substrate, providing at least one graphene catalyst 4 material at a substrate region that is specified for synthesizing a graphene 5 transistor channel, the gra p hene transistor channel catal y st having a first 6 carbon solubility; 7 on the fabrication substrate, providing at least one graphene 8 catalyst material at a substrate region that is specified for synthesizing a 9 graphene transistor source-and at a substrate region that is specified for 10 synthesizing a graphene transistor drain s each of the grap hene transistor 11 source and drain catalyst materials having a carbon solubility that is 12 different than the first carbon solubility; 13 in one graphene synthesis step, forming at least one layer of 14 graphene at the substrate region specified for the graphene transistor 15 channel, and forming at the region specified for the transistor source and 16 the region specified for the transistor drain a plurality of layers of 17 graphene that is greater than the at least one la y er of grap hene of the 18 transistor channel. 1
The method of claim 11 further comprising: 2 applying a layer of a gate dielectric over the formed graphene layers; 3 and 4 forming a graphene transistor gate of a plurality of layers of graphene on the gate dielectric layer. -4- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668757.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 13. The method of claim 11 further comprising: 2 applying a layer of handle material on the formed graphene layers; 3 removing the plurality of catalyst materials and the fabrication 4 substrate from the formed graphene layers; and 5 applying the graphene layers, in a pattern of the transistor channel, 6 transistor source region, and transistor drain region, onto an operational 7 substrate. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 channel comprises Cu and Ni. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 source and a graphene transistor drain comprises Co, Cu, and Ni. 1
The method claim 11 wherein forming at the region 2 specified for the transistor source and the region specified for the 3 transistor drain a plurality of layers of graphene comprises forming at 4 least about 800 l ayers of graphene. 1
The method of claim 11 wherein providing at least one 2 graphene catalyst material at a substrate region comprises providing a 3 graphene transistor channel catalyst region of a first thickness; and 4 wherein providing a graphene catalyst material at a substrate 5 region that is specified for synthesizing a graphene transistor source and 6 providing a graphene catalyst material at a substrate region that is 7 specified for synthesizing a graphene transistor drain comprises providing 8 a graphene transistor source catalyst region and a graphene transistor 9 drain catalyst region each of a second thickness that is greater than the 10 first thickness. -8-
The method of claim 13 wherein the operational 2 substrate comprises a silicon wafer. 1
The method of claim 13 wherein the operational 2 substrate comprises a mechanically flexible, non-rigid material. -5- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 19. The method of claim 13 wherein the operational 2 substrate includes a layer of dielectric material, and further comprising 3 making electrical connection to the operational substrate as a transistor 4 back gate. 1
The method of claim 13 wherein applying the graphene 2 layers, in a pattern of the transistor channel, transistor source, and 3 transistor drain regions, onto an operational substrate comprises applying 4 a plurality of patterns of transistor channel, transistor source, and 5 transistor drain regions onto an operation substrate in an array of 6 graphene transistors. 1
A graphene transistor comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; and 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one layer of grap hene of the transistor channel. 1
The graphene transistor of claim 21 wherein the 2 substrate is electrically conducting and includes a dielectric layer on which 3 the transistor channel, source, and drain are disposed, and is connected as 4 a back gate for the graphene transistor. 1 23. The graphene transistor of claim 21 further comprising: SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.27.280.2854.2125.2944.svg 0.3 6.15 Graph Black and white -6- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668759.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 3 a graphene transistor gate that is disposed on the dielectric layer 4 and comprising a plurality of layers of graphene, and that is connected as a 5 top gate for the graphene transistor. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a flexible, non-rigid material. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a silicon substrate including a layer of silicon dioxide. 1
The graphene transistor of claim 21 wherein the 2 transistor source and transistor drain each comprise a number of layers of 3 graphene that is greater than about 800 layers. 1
The graphene transistor of claim 21 wherein the 2 transistor channel comprises about 1-3 layers of graphene. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a material selected from semitransparent materials 3 and transparent materials. 1
A graphene circuit comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and -7- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668760.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one la y er of gra p hene of the transistor channel; and 9 electrical interconnections to the transistor source and drain, each 10 interconnection comprising a plurality of layers of graphene. 1
The graphene circuit of claim 29 wherein the substrate 2 comprises a silicon substrate including a layer of silicon dioxide. 1
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene circuit
Materials described outside the worked examples.
graphene
graphene synthesis catalyst material
methane gas
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,836Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a graphene structure 2 c omprising: 3 on a fabrication substrate, forming a pattern of a plurality of 4 gra p hene synthesis catal y st regions, each of the gra p hene synthesis 5 catal y st re g ions in the plurality includin g a different di stmet- graphene 6 c atalyst materia lmater als, and each of the different grap hene catalys t 7 materials havin g a different carbon solubility; and 8 in one graphene synthesis step, ex p osing the different gra p hene 9 c atalyst materials of the p lurality of gra p hene synthesis catal y st regions 10 to a source of carbon, formin g a different number mwber- of graphene 11 layers on the different g raphene catalyst materials in the formed pattern. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises exposure of the graphene catalyst materials to a 3 c arbonaceous gas. 1
The method of claim 1 wherein the graphene synthesis 2 step comprises chemical vapor deposition with methane gas. -2- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.2.1399.207.2247.292.svg 0.283 2.827 Chemistry Black and white Serial No. 13/817,885 1 5. The method of claim 1 wherein the plurality of gra p hene 2 synthesis catal y st regions having different di stinet-graphene catalyst 3 materials com p rise ineludm a ralit f m aterials selected from the 4 g rou p consisting of Co, Cu, Fe, Ge, A l, Ni, Pd, Pt, and Au, alloys thereof, 5 and layered combinations thereof. 1
The method of claim 1 wherein the different plura1ity-ef 2 di se-t-graphene catalyst materials include Iel-des a layered 3 combination of Cu and Ni. 1
The method of claim 1 wherein the different p lrality-ef 2 di et-i-net- graphene catalyst materials include Iemades a layered 3 combination of Cu, Ni, and Co. 1
The method of claim 1 wherein the different pl-a1ity-ef 2 4ie-t- graphene catalyst materials include irelude Cu, Ni, and Co. 1
The method of claim 1 further comprising: 2 applying a layer of handle material on the formed graphene layers; SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.19.281.2223.2039.2313.svg 0.3 5.86 Graph Black and white 4 fabrication substrate from the formed graphene layers; and 5 applying the graphene layers, in the formed pattern, onto an 6 operational substrate. 1 10. The method of claim 1 wherein forming a pattern SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668755.24.280.2764.2223.2854.svg 0.3 6.477 Graph Black and white -3- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668756.4.281.420.2213.510.svg 0.3 6.44 Graph Black and white Serial No. 13/817,885 4 graphene electrical connections to the device. 1
The method of claim 1 wherein each in the plurality of 2 graphene synthesis catalyst regions having a different graphene catalyst 3 material has a different catalyst material thickness. 1
A method for fabricating a graphene transistor 2 comprising: 3 on a fabrication substrate, providing at least one graphene catalyst 4 material at a substrate region that is specified for synthesizing a graphene 5 transistor channel, the gra p hene transistor channel catal y st having a first 6 carbon solubility; 7 on the fabrication substrate, providing at least one graphene 8 catalyst material at a substrate region that is specified for synthesizing a 9 graphene transistor source-and at a substrate region that is specified for 10 synthesizing a graphene transistor drain s each of the grap hene transistor 11 source and drain catalyst materials having a carbon solubility that is 12 different than the first carbon solubility; 13 in one graphene synthesis step, forming at least one layer of 14 graphene at the substrate region specified for the graphene transistor 15 channel, and forming at the region specified for the transistor source and 16 the region specified for the transistor drain a plurality of layers of 17 graphene that is greater than the at least one la y er of grap hene of the 18 transistor channel. 1
The method of claim 11 further comprising: 2 applying a layer of a gate dielectric over the formed graphene layers; 3 and 4 forming a graphene transistor gate of a plurality of layers of graphene on the gate dielectric layer. -4- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668757.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 13. The method of claim 11 further comprising: 2 applying a layer of handle material on the formed graphene layers; 3 removing the plurality of catalyst materials and the fabrication 4 substrate from the formed graphene layers; and 5 applying the graphene layers, in a pattern of the transistor channel, 6 transistor source region, and transistor drain region, onto an operational 7 substrate. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 channel comprises Cu and Ni. 1
The method of claim 11 wherein the at least one 2 graphene catalyst material provided for synthesizing a graphene transistor 3 source and a graphene transistor drain comprises Co, Cu, and Ni. 1
The method claim 11 wherein forming at the region 2 specified for the transistor source and the region specified for the 3 transistor drain a plurality of layers of graphene comprises forming at 4 least about 800 l ayers of graphene. 1
The method of claim 11 wherein providing at least one 2 graphene catalyst material at a substrate region comprises providing a 3 graphene transistor channel catalyst region of a first thickness; and 4 wherein providing a graphene catalyst material at a substrate 5 region that is specified for synthesizing a graphene transistor source and 6 providing a graphene catalyst material at a substrate region that is 7 specified for synthesizing a graphene transistor drain comprises providing 8 a graphene transistor source catalyst region and a graphene transistor 9 drain catalyst region each of a second thickness that is greater than the 10 first thickness. -8-
The method of claim 13 wherein the operational 2 substrate comprises a silicon wafer. 1
The method of claim 13 wherein the operational 2 substrate comprises a mechanically flexible, non-rigid material. -5- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 1 19. The method of claim 13 wherein the operational 2 substrate includes a layer of dielectric material, and further comprising 3 making electrical connection to the operational substrate as a transistor 4 back gate. 1
The method of claim 13 wherein applying the graphene 2 layers, in a pattern of the transistor channel, transistor source, and 3 transistor drain regions, onto an operational substrate comprises applying 4 a plurality of patterns of transistor channel, transistor source, and 5 transistor drain regions onto an operation substrate in an array of 6 graphene transistors. 1
A graphene transistor comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; and 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one layer of grap hene of the transistor channel. 1
The graphene transistor of claim 21 wherein the 2 substrate is electrically conducting and includes a dielectric layer on which 3 the transistor channel, source, and drain are disposed, and is connected as 4 a back gate for the graphene transistor. 1 23. The graphene transistor of claim 21 further comprising: SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668758.27.280.2854.2125.2944.svg 0.3 6.15 Graph Black and white -6- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668759.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 3 a graphene transistor gate that is disposed on the dielectric layer 4 and comprising a plurality of layers of graphene, and that is connected as a 5 top gate for the graphene transistor. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a flexible, non-rigid material. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a silicon substrate including a layer of silicon dioxide. 1
The graphene transistor of claim 21 wherein the 2 transistor source and transistor drain each comprise a number of layers of 3 graphene that is greater than about 800 layers. 1
The graphene transistor of claim 21 wherein the 2 transistor channel comprises about 1-3 layers of graphene. 1
The graphene transistor of claim 21 wherein the 2 substrate comprises a material selected from semitransparent materials 3 and transparent materials. 1
A graphene circuit comprising: 2 a substrate; 3 a graphene transistor channel disposed on the substrate and 4 comprising at least one layer of graphene; 5 a transistor source and a transistor drain, each of which is 6 c onnected to the transistor channel and disposed on the substrate, and -7- SVG 13817885.11-17-2014.I₂MOCM₈SPXXIFW3.CLM1668760.2.1399.207.2247.292.svg 0.283 2.827 Graph Black and white Serial No. 13/817,885 7 each comprising a plurality of layers of graphene that is greater than the 8 at least one la y er of gra p hene of the transistor channel; and 9 electrical interconnections to the transistor source and drain, each 10 interconnection comprising a plurality of layers of graphene. 1
The graphene circuit of claim 29 wherein the substrate 2 comprises a silicon substrate including a layer of silicon dioxide. 1
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene circuit
Materials described outside the worked examples.
graphene
graphene synthesis catalyst material
methane gas
Related documents with shared materials, methods, properties, or citations.
graphene catalyst materials group: Co, Cu, Fe, Ge, Al, Ni, Pd, Pt, Au, alloys thereof, and layered combinations thereof
Cu
Ni
Co
silicon
Si
silicon dioxide
SiO₂
METHOD AND SYSTEM FOR PRODUCING GRAPHENE AND FUNCTIONALIZED GRAPHENE
graphene catalyst materials group: Co, Cu, Fe, Ge, Al, Ni, Pd, Pt, Au, alloys thereof, and layered combinations thereof
Cu
Ni
Co
silicon
Si
silicon dioxide
SiO₂
METHOD AND SYSTEM FOR PRODUCING GRAPHENE AND FUNCTIONALIZED GRAPHENE
graphene catalyst materials group: Co, Cu, Fe, Ge, Al, Ni, Pd, Pt, Au, alloys thereof, and layered combinations thereof
Cu
Ni
Co
silicon
Si
silicon dioxide
SiO₂
METHOD AND SYSTEM FOR PRODUCING GRAPHENE AND FUNCTIONALIZED GRAPHENE
graphene catalyst materials group: Co, Cu, Fe, Ge, Al, Ni, Pd, Pt, Au, alloys thereof, and layered combinations thereof
Cu
Ni
Co
silicon
Si
silicon dioxide
SiO₂