Patent
US 9,142,639GRAPHENE ELECTRONIC DEVICES AND METHODS OF MANUFACTURING THE SAME
Yong-sung KIM
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,142,639Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B is a schematic plan view of the graphene electronic device of
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
FIGS. 3A through 3D are diagrams illustrating an example embodiment of a method of manufacturing the graphene electronic device shown in
FIG. 4 is a cross-sectional view of an example embodiment of a ferroelectric memory device including graphene; [0031]
FIG. 5 is a cross-sectional view of an example embodiment of a flash memory device including graphene; and [0032]
FIG. 6 is a cross-sectional view of an example embodiment of a hybrid-type memory device including graphene.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.
The device of claim 1, wherein the first gate structure corresponds to the first region of the intermediate layer.
The device of claim 1, wherein the second gate structure corresponds to a space between the first region and the second region of the intermediate layer.
The device of claim 1, wherein the intermediate layer is on a support structure.
The device of claim 1, wherein the first gate structure includes a gate insulating layer and a first gate. 2 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.1.145.144.2220.243.svg 0.33 6.917 Graph Black and white
The device of claim 1, wherein the first gate structure includes a first ferroelectric layer and a first gate. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.7.166.937.2219.995.svg 0.193 6.843 Chemistry Black and white includes a second ferroelectric layer and a second gate. withdrawn
The device of claim 1, wherein the first gate structure includes a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate. withdrawn
The device of claim 1, wherein the graphene layer is on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the first gate structure and the second gate structure are spaced apart from each other on top of the graphene layer. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173292.18.439.1791.2491.1847.svg 0.187 6.84 Graph Black and white the forming the graphene layer includes forming the graphene layer on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the forming the first gate structure and the second gate structure includes forming the first gate structure and the second gate structure spaced apart from each other on top of the graphene layer.
A method of forming a graphene electronic device, the method comprising: forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate; forming an intermediate layer on the substrate, the semiconductor layer, the first conductive layer, and the second conductive layer; forming a graphene layer on the intermediate layer, the semiconductor layer, SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.27.307.2866.2478.2922.svg 0.187 7.237 Graph Black and white forming a first gate structure and a second gate structure on the graphene layer. 3 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173290.4.150.144.2227.243.svg 0.33 6.923 Graph Black and white
The method of claim 11, further comprising: forming a support structure on the intermediate layer.
The method of claim 11, further comprising: removing the substrate.
The device of claim 11, wherein the graphene layer is formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method.
A graphene electronic device comprising: a graphene transistor having a channel including a graphene layer and an electrode including a semiconductor layer; and a graphene tunable diode having a diode region including the graphene layer and the semiconductor layer.
The device of claim 17, wherein the graphene transistor comprises: 4 Atty. Dkt. No. 2557S I -001983-US U.S. Application No. 13/975,680 a first conductive layer and the semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; the graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a gate structure on the graphene layer.
The device of claim 17, wherein the graphene tunable diode comp ri ses: the semiconductor layer on a first region of an intermediate layer; the graphene layer on the intermediate layer and the semiconductor-layer; and a gate structure on the graphene layer corresponding to the first region of the intermediate layer.
The device of claim 17, further comprising: a first gate structure corresponding to the graphene transistor; and a second gate structure corresponding to the graphene tunable diode.
The device of claim 17, wherein the device includes a first gate structure and a second gate structure spaced 6 Atty. Dkt. No. 2557S I-00 1983-US U.S. Application No. 13/975,680 apart from each other on top of the graphene layer, and the graphene layer is on top of the semiconductor layer. 7
Layer stacks claimed or described, ordered top of device to substrate.
graphene electronic device
Materials described outside the worked examples.
graphene
semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,142,639Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B is a schematic plan view of the graphene electronic device of
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
FIGS. 3A through 3D are diagrams illustrating an example embodiment of a method of manufacturing the graphene electronic device shown in
FIG. 4 is a cross-sectional view of an example embodiment of a ferroelectric memory device including graphene; [0031]
FIG. 5 is a cross-sectional view of an example embodiment of a flash memory device including graphene; and [0032]
FIG. 6 is a cross-sectional view of an example embodiment of a hybrid-type memory device including graphene.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.
The device of claim 1, wherein the first gate structure corresponds to the first region of the intermediate layer.
The device of claim 1, wherein the second gate structure corresponds to a space between the first region and the second region of the intermediate layer.
The device of claim 1, wherein the intermediate layer is on a support structure.
The device of claim 1, wherein the first gate structure includes a gate insulating layer and a first gate. 2 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.1.145.144.2220.243.svg 0.33 6.917 Graph Black and white
The device of claim 1, wherein the first gate structure includes a first ferroelectric layer and a first gate. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.7.166.937.2219.995.svg 0.193 6.843 Chemistry Black and white includes a second ferroelectric layer and a second gate. withdrawn
The device of claim 1, wherein the first gate structure includes a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate. withdrawn
The device of claim 1, wherein the graphene layer is on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the first gate structure and the second gate structure are spaced apart from each other on top of the graphene layer. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173292.18.439.1791.2491.1847.svg 0.187 6.84 Graph Black and white the forming the graphene layer includes forming the graphene layer on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the forming the first gate structure and the second gate structure includes forming the first gate structure and the second gate structure spaced apart from each other on top of the graphene layer.
A method of forming a graphene electronic device, the method comprising: forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate; forming an intermediate layer on the substrate, the semiconductor layer, the first conductive layer, and the second conductive layer; forming a graphene layer on the intermediate layer, the semiconductor layer, SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.27.307.2866.2478.2922.svg 0.187 7.237 Graph Black and white forming a first gate structure and a second gate structure on the graphene layer. 3 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173290.4.150.144.2227.243.svg 0.33 6.923 Graph Black and white
The method of claim 11, further comprising: forming a support structure on the intermediate layer.
The method of claim 11, further comprising: removing the substrate.
The device of claim 11, wherein the graphene layer is formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method.
A graphene electronic device comprising: a graphene transistor having a channel including a graphene layer and an electrode including a semiconductor layer; and a graphene tunable diode having a diode region including the graphene layer and the semiconductor layer.
The device of claim 17, wherein the graphene transistor comprises: 4 Atty. Dkt. No. 2557S I -001983-US U.S. Application No. 13/975,680 a first conductive layer and the semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; the graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a gate structure on the graphene layer.
The device of claim 17, wherein the graphene tunable diode comp ri ses: the semiconductor layer on a first region of an intermediate layer; the graphene layer on the intermediate layer and the semiconductor-layer; and a gate structure on the graphene layer corresponding to the first region of the intermediate layer.
The device of claim 17, further comprising: a first gate structure corresponding to the graphene transistor; and a second gate structure corresponding to the graphene tunable diode.
The device of claim 17, wherein the device includes a first gate structure and a second gate structure spaced 6 Atty. Dkt. No. 2557S I-00 1983-US U.S. Application No. 13/975,680 apart from each other on top of the graphene layer, and the graphene layer is on top of the semiconductor layer. 7
Layer stacks claimed or described, ordered top of device to substrate.
graphene electronic device
Materials described outside the worked examples.
graphene
semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,142,639Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B is a schematic plan view of the graphene electronic device of
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
FIGS. 3A through 3D are diagrams illustrating an example embodiment of a method of manufacturing the graphene electronic device shown in
FIG. 4 is a cross-sectional view of an example embodiment of a ferroelectric memory device including graphene; [0031]
FIG. 5 is a cross-sectional view of an example embodiment of a flash memory device including graphene; and [0032]
FIG. 6 is a cross-sectional view of an example embodiment of a hybrid-type memory device including graphene.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.
The device of claim 1, wherein the first gate structure corresponds to the first region of the intermediate layer.
The device of claim 1, wherein the second gate structure corresponds to a space between the first region and the second region of the intermediate layer.
The device of claim 1, wherein the intermediate layer is on a support structure.
The device of claim 1, wherein the first gate structure includes a gate insulating layer and a first gate. 2 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.1.145.144.2220.243.svg 0.33 6.917 Graph Black and white
The device of claim 1, wherein the first gate structure includes a first ferroelectric layer and a first gate. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.7.166.937.2219.995.svg 0.193 6.843 Chemistry Black and white includes a second ferroelectric layer and a second gate. withdrawn
The device of claim 1, wherein the first gate structure includes a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate. withdrawn
The device of claim 1, wherein the graphene layer is on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the first gate structure and the second gate structure are spaced apart from each other on top of the graphene layer. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173292.18.439.1791.2491.1847.svg 0.187 6.84 Graph Black and white the forming the graphene layer includes forming the graphene layer on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the forming the first gate structure and the second gate structure includes forming the first gate structure and the second gate structure spaced apart from each other on top of the graphene layer.
A method of forming a graphene electronic device, the method comprising: forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate; forming an intermediate layer on the substrate, the semiconductor layer, the first conductive layer, and the second conductive layer; forming a graphene layer on the intermediate layer, the semiconductor layer, SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.27.307.2866.2478.2922.svg 0.187 7.237 Graph Black and white forming a first gate structure and a second gate structure on the graphene layer. 3 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173290.4.150.144.2227.243.svg 0.33 6.923 Graph Black and white
The method of claim 11, further comprising: forming a support structure on the intermediate layer.
The method of claim 11, further comprising: removing the substrate.
The device of claim 11, wherein the graphene layer is formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method.
A graphene electronic device comprising: a graphene transistor having a channel including a graphene layer and an electrode including a semiconductor layer; and a graphene tunable diode having a diode region including the graphene layer and the semiconductor layer.
The device of claim 17, wherein the graphene transistor comprises: 4 Atty. Dkt. No. 2557S I -001983-US U.S. Application No. 13/975,680 a first conductive layer and the semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; the graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a gate structure on the graphene layer.
The device of claim 17, wherein the graphene tunable diode comp ri ses: the semiconductor layer on a first region of an intermediate layer; the graphene layer on the intermediate layer and the semiconductor-layer; and a gate structure on the graphene layer corresponding to the first region of the intermediate layer.
The device of claim 17, further comprising: a first gate structure corresponding to the graphene transistor; and a second gate structure corresponding to the graphene tunable diode.
The device of claim 17, wherein the device includes a first gate structure and a second gate structure spaced 6 Atty. Dkt. No. 2557S I-00 1983-US U.S. Application No. 13/975,680 apart from each other on top of the graphene layer, and the graphene layer is on top of the semiconductor layer. 7
Layer stacks claimed or described, ordered top of device to substrate.
graphene electronic device
Materials described outside the worked examples.
graphene
semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,142,639Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B is a schematic plan view of the graphene electronic device of
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
FIGS. 3A through 3D are diagrams illustrating an example embodiment of a method of manufacturing the graphene electronic device shown in
FIG. 4 is a cross-sectional view of an example embodiment of a ferroelectric memory device including graphene; [0031]
FIG. 5 is a cross-sectional view of an example embodiment of a flash memory device including graphene; and [0032]
FIG. 6 is a cross-sectional view of an example embodiment of a hybrid-type memory device including graphene.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.
The device of claim 1, wherein the first gate structure corresponds to the first region of the intermediate layer.
The device of claim 1, wherein the second gate structure corresponds to a space between the first region and the second region of the intermediate layer.
The device of claim 1, wherein the intermediate layer is on a support structure.
The device of claim 1, wherein the first gate structure includes a gate insulating layer and a first gate. 2 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.1.145.144.2220.243.svg 0.33 6.917 Graph Black and white
The device of claim 1, wherein the first gate structure includes a first ferroelectric layer and a first gate. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.7.166.937.2219.995.svg 0.193 6.843 Chemistry Black and white includes a second ferroelectric layer and a second gate. withdrawn
The device of claim 1, wherein the first gate structure includes a first tunneling oxide layer, a first floating gate, a first blocking oxide layer, and a first gate. withdrawn
The device of claim 1, wherein the graphene layer is on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the first gate structure and the second gate structure are spaced apart from each other on top of the graphene layer. SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173292.18.439.1791.2491.1847.svg 0.187 6.84 Graph Black and white the forming the graphene layer includes forming the graphene layer on top of the intermediate layer, the semiconductor layer, and the second conductive layer, the first conductive layer is between the intermediate layer and the graphene layer, the semiconductor layer is between the first conductive layer and the graphene layer, and the forming the first gate structure and the second gate structure includes forming the first gate structure and the second gate structure spaced apart from each other on top of the graphene layer.
A method of forming a graphene electronic device, the method comprising: forming a semiconductor layer, a first conductive layer, and a second conductive layer on a substrate; forming an intermediate layer on the substrate, the semiconductor layer, the first conductive layer, and the second conductive layer; forming a graphene layer on the intermediate layer, the semiconductor layer, SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173289.27.307.2866.2478.2922.svg 0.187 7.237 Graph Black and white forming a first gate structure and a second gate structure on the graphene layer. 3 SVG 13975680.03-06-2015.I₇₇UXYAKPXXIFW4.CLM12173290.4.150.144.2227.243.svg 0.33 6.923 Graph Black and white
The method of claim 11, further comprising: forming a support structure on the intermediate layer.
The method of claim 11, further comprising: removing the substrate.
The device of claim 11, wherein the graphene layer is formed on a catalyst layer by a pyrolisis method or a chemical vapor deposition (CVD) method.
A graphene electronic device comprising: a graphene transistor having a channel including a graphene layer and an electrode including a semiconductor layer; and a graphene tunable diode having a diode region including the graphene layer and the semiconductor layer.
The device of claim 17, wherein the graphene transistor comprises: 4 Atty. Dkt. No. 2557S I -001983-US U.S. Application No. 13/975,680 a first conductive layer and the semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; the graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a gate structure on the graphene layer.
The device of claim 17, wherein the graphene tunable diode comp ri ses: the semiconductor layer on a first region of an intermediate layer; the graphene layer on the intermediate layer and the semiconductor-layer; and a gate structure on the graphene layer corresponding to the first region of the intermediate layer.
The device of claim 17, further comprising: a first gate structure corresponding to the graphene transistor; and a second gate structure corresponding to the graphene tunable diode.
The device of claim 17, wherein the device includes a first gate structure and a second gate structure spaced 6 Atty. Dkt. No. 2557S I-00 1983-US U.S. Application No. 13/975,680 apart from each other on top of the graphene layer, and the graphene layer is on top of the semiconductor layer. 7
Layer stacks claimed or described, ordered top of device to substrate.
graphene electronic device
Materials described outside the worked examples.
graphene
semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
Related documents with shared materials, methods, properties, or citations.
graphene transistor
graphene tunable diode
silicon
Si
silicon oxide
SiO₂
copper
Cu
nickel
Ni
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
METHODS OF FABRICATION OF GRAPHENE NANORIBBONS
graphene transistor
graphene tunable diode
silicon
Si
silicon oxide
SiO₂
copper
Cu
nickel
Ni
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
METHODS OF FABRICATION OF GRAPHENE NANORIBBONS
graphene transistor
graphene tunable diode
silicon
Si
silicon oxide
SiO₂
copper
Cu
nickel
Ni
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]
METHODS OF FABRICATION OF GRAPHENE NANORIBBONS
graphene transistor
graphene tunable diode
silicon
Si
silicon oxide
SiO₂
copper
Cu
nickel
Ni
FIG. 2 is a graph showing electrical characteristics of the graphene electronic device according to an example embodiment; [0029]