Patent
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a GaN die comprising a lateral GaN transistor, the GaN die being sandwiched between an overlying header and an underlying composite thermal dielectric layer; the GaN die comprising: a conductive metallization layer formed thereon one of more layers of on-chip metallization being provided on a front side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front side of the epi layer stack; and overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front side of the GaN die; the overlying header comprising: a support layer substrate comprising a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack and a conductive metallization layer formed on the support layer substrate defining conductive tracks for source, drain and gate interconnections; the overlying header being attached to the GaN die by low inductance conductive interconnections between contact areas of said conductive tracks and respective the contact pads of the source, drain and gate pads electrodes of the lateral GaN transistor and corresponding source, drain and gate contact areas of the conductive tracks of the overlying header; and a conductive layer provided on a back-side of the GaN-epilayer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 2 the composite thermal dielectric layer comprising: a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprising one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride, Aluminum Nitride, Silicon Nitride, diamond, and mixtures thereof, the composite thermal dielectric layer forming a coating on [[a]] the back-side of the G aN epi-layer stack and the one or more back-side field plates, and wherein the composite thermal dielectric has a dielectric strength of at least 40V/pm and a thermal conductivity of about 2W/m.K or more, and the composite thermal dielectric layer has a thickness that provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting of a micro- particulate form of Boron Nitride, Aluminum Nitride, Silicon Nitride, and diamond, and said micro-particulate form comprising micro-particles, micro-flakes, micro-platelets, micro-fibers, nano- particles, nano-platelets, nano-tubes, nano-fibers, and mixtures thereof.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting: Boron Nitride Nano-Tubes (BNNT); Cubic boron nitride powder (c-BN), Boron Nitride nano-particles; hexagonal Boron Nitride flakes (h-BN); and mixtures thereof.
The device of claim 1, wherein the composite thermal dielectric has a dielectric strength of at least 100 V/pm and a thermal conductivity in the range from about 2 W/m.K to 5 W/m.K, and the composite thermal dielectric layer has a thickness in the range from 10 p m to 50 p m and is characterized by a breakdown strength which provides a breakdown voltage in the range from 850V to 2000V and a thermal resistance of less than 1 0 C/W.
The device structure of claim 1, wherein the composite thermal dielectric layer comprises one or more spin-coated layers.
The device structure of claim 1, further comprising a heatspreader layer of a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C), the heatspreader layer being bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising a heatspreader comprising a thermally conductive layer of a ceramic, a metal or a metal alloy, the heatspreader being adhesively bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising external front-side source, drain and gate contact pads for each of the source, drain and gate interconnections provided on an external surface of the support layer substrate of the header, and low inductance conductive vias extending through the support layer substrate from said external front-side source, drain and gate contact areas pads to the 4 respective source, drain and gate contact areas of the conductive metallization layer formed on the support layer substrate of the header.
(Withdrawn-Currently Amended) A method of fabricating the nitride semiconductor device of claim 1, comprising: providing a GaN die comprising a silicon growth substrate having formed thereon a GaN epi-layer stack; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active layer for a lateral GaN transistor and at least one underlying layer comprising a buffer layer or an intermediate layer; [[a]] providing on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, one or more layers of on-chip metallization layer formed on the GaN epi layer stack defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front face of the epi layer stack and the GaN die comprising overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front face of the GaN die, providing a header comprising a support layer substrate of dielectric material having a CTE closely matched to the CTE of the GaN epi-layer stack, and a conductive metallization layer formed on the support layer substrate defining conductive tracks and contact areas for source, drain and gate interconnections, said contact areas for source, drain and gate interconnections having an arrangement for alignment and interconnection with respective the source, drain and gate pads of the GaN die; aligning and assembling the GaN die and the header by providing low inductance conductive interconnections mechanically and electrically interconnecting the source, drain and gate pads of the GaN die with the corresponding source, drain and gate contact areas of conductive tracks of the header; removing the growth substrate from the backside of the epi-layer stack to expose a substrate surface back- side of the GaN epi-layer stack comprising an underlying buffer layer or intermediate layer of the GaN epi-layer stack, the GaN die then being supported by the header; and providing a conductive layer on the back-side of the GaN epi-layer stack, said conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 5 applying a composite thermal dielectric layer on the substrate surface back-side of the GaN epi-layer stack and the one or more back-side field plates, the composite thermal dielectric layer comprising a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprisin g one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C) and wherein the composite thermal dielectric layer has a dielectric strength of at least 40V/m and a thermal conductivity of about 2W/m.K or more, such that a thickness of 10pm to 50 m provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
canceled
canceled
The device structure of claim 10 claim 1, wherein the conductive layer on formed on the composite thermal dielectric layer defining the one or more back-side field plates comprises a metal filled thermoplastic polyimide material.
canceled
canceled
(New-Withdrawn) A nitride semiconductor device structure comprising: a GaN epi-layer stack sandwiched between an overlying dielectric support substrate and an underlying, relatively thin dielectric thermal layer; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active region for a lateral GaN transistor and one or more underlying intermediate layers or buffer layers; at least one layer of on-chip metallization provided on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the plurality of lateral GaN transistors, a gate electrode formed on a channel region between the source and drain electrodes, and external contact pads for the source, drain and gate electrodes; the overlying support substrate comprising a layer of a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack, and the support substrate comprising a layer of conductive metallization defining conductive tracks for source, drain and gate interconnections; the external source, drain and gate pads of the lateral GaN transistor being mechanically and electrically interconnected by low inductance interconnections to corresponding source, drain and gate contact areas of 7 said conductive tracks of the overlying support substrate, and dielectric underfill filling gaps between said low inductance interconnections; a conductive layer formed on a back-side of the GaN the epi-layer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; a thermal dielectric layer applied on the back-side of the GaN epi-layer stack and the back-side field plates, the thermal dielectric layer comprising a material having a high thermal conductivity, a CTE closely matched to CTE of the GaN epi-layer stack, and a dielectric strength of at least 4 0V/p m, whereby a layer thickness of the thermal dielectric layer having a thickness of approximately 50 p m provides a breakdown voltage of at least 1000V. withdrawn
(New- withdrawn) A nitride semiconductor device structure of claim 23 wherein the thermal dielectric layer comprises a layer of aluminum nitride or a layer of boron nitride. 8 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN transistor (GaN HEMT) with back-side field plates and composite thermal dielectric
Materials described outside the worked examples.
GaN epi-layer stack
GaN/AlGaN hetero-layer structure
polyimide or epoxy (high dielectric strength polymer dielectric)
composite thermal dielectric layer
Boron Nitride
BN
Aluminum Nitride
AlN
Silicon Nitride
Si₃N₄
thermoplastic polyimide (TPI)
diamond
C
metal filled thermoplastic polyimide
silicon substrate (growth substrate)
Si
ceramic dielectric support layer (header)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
composite thermal dielectric minimum dielectric strength (claim 1) | 40 V/um | composite thermal dielectric layer |
composite thermal dielectric minimum thermal conductivity (claim 1) | 2 W/m.K | composite thermal dielectric layer |
composite thermal dielectric minimum breakdown voltage (claim 1) | 850 V | composite thermal dielectric layer |
composite thermal dielectric maximum thermal resistance (claim 1) | 1 C/W | composite thermal dielectric layer |
composite thermal dielectric minimum dielectric strength (claim 4) | 100 V/um | composite thermal dielectric layer |
composite thermal dielectric thermal conductivity range (claim 4) | 2–5 W/m.K | composite thermal dielectric layer |
composite thermal dielectric breakdown voltage range (claim 4) | 850–2000 V | composite thermal dielectric layer |
— | 2–5 W | — |
Temperature | 200–300 °C | — |
Thickness | 10–50 µm | — |
— | 1.8–2.5 W | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1 V | — |
Temperature | ≤ 1 °C | — |
Voltage | ≥ 40 V | — |
Voltage | ≥ 850 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a GaN die comprising a lateral GaN transistor, the GaN die being sandwiched between an overlying header and an underlying composite thermal dielectric layer; the GaN die comprising: a conductive metallization layer formed thereon one of more layers of on-chip metallization being provided on a front side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front side of the epi layer stack; and overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front side of the GaN die; the overlying header comprising: a support layer substrate comprising a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack and a conductive metallization layer formed on the support layer substrate defining conductive tracks for source, drain and gate interconnections; the overlying header being attached to the GaN die by low inductance conductive interconnections between contact areas of said conductive tracks and respective the contact pads of the source, drain and gate pads electrodes of the lateral GaN transistor and corresponding source, drain and gate contact areas of the conductive tracks of the overlying header; and a conductive layer provided on a back-side of the GaN-epilayer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 2 the composite thermal dielectric layer comprising: a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprising one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride, Aluminum Nitride, Silicon Nitride, diamond, and mixtures thereof, the composite thermal dielectric layer forming a coating on [[a]] the back-side of the G aN epi-layer stack and the one or more back-side field plates, and wherein the composite thermal dielectric has a dielectric strength of at least 40V/pm and a thermal conductivity of about 2W/m.K or more, and the composite thermal dielectric layer has a thickness that provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting of a micro- particulate form of Boron Nitride, Aluminum Nitride, Silicon Nitride, and diamond, and said micro-particulate form comprising micro-particles, micro-flakes, micro-platelets, micro-fibers, nano- particles, nano-platelets, nano-tubes, nano-fibers, and mixtures thereof.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting: Boron Nitride Nano-Tubes (BNNT); Cubic boron nitride powder (c-BN), Boron Nitride nano-particles; hexagonal Boron Nitride flakes (h-BN); and mixtures thereof.
The device of claim 1, wherein the composite thermal dielectric has a dielectric strength of at least 100 V/pm and a thermal conductivity in the range from about 2 W/m.K to 5 W/m.K, and the composite thermal dielectric layer has a thickness in the range from 10 p m to 50 p m and is characterized by a breakdown strength which provides a breakdown voltage in the range from 850V to 2000V and a thermal resistance of less than 1 0 C/W.
The device structure of claim 1, wherein the composite thermal dielectric layer comprises one or more spin-coated layers.
The device structure of claim 1, further comprising a heatspreader layer of a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C), the heatspreader layer being bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising a heatspreader comprising a thermally conductive layer of a ceramic, a metal or a metal alloy, the heatspreader being adhesively bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising external front-side source, drain and gate contact pads for each of the source, drain and gate interconnections provided on an external surface of the support layer substrate of the header, and low inductance conductive vias extending through the support layer substrate from said external front-side source, drain and gate contact areas pads to the 4 respective source, drain and gate contact areas of the conductive metallization layer formed on the support layer substrate of the header.
(Withdrawn-Currently Amended) A method of fabricating the nitride semiconductor device of claim 1, comprising: providing a GaN die comprising a silicon growth substrate having formed thereon a GaN epi-layer stack; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active layer for a lateral GaN transistor and at least one underlying layer comprising a buffer layer or an intermediate layer; [[a]] providing on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, one or more layers of on-chip metallization layer formed on the GaN epi layer stack defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front face of the epi layer stack and the GaN die comprising overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front face of the GaN die, providing a header comprising a support layer substrate of dielectric material having a CTE closely matched to the CTE of the GaN epi-layer stack, and a conductive metallization layer formed on the support layer substrate defining conductive tracks and contact areas for source, drain and gate interconnections, said contact areas for source, drain and gate interconnections having an arrangement for alignment and interconnection with respective the source, drain and gate pads of the GaN die; aligning and assembling the GaN die and the header by providing low inductance conductive interconnections mechanically and electrically interconnecting the source, drain and gate pads of the GaN die with the corresponding source, drain and gate contact areas of conductive tracks of the header; removing the growth substrate from the backside of the epi-layer stack to expose a substrate surface back- side of the GaN epi-layer stack comprising an underlying buffer layer or intermediate layer of the GaN epi-layer stack, the GaN die then being supported by the header; and providing a conductive layer on the back-side of the GaN epi-layer stack, said conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 5 applying a composite thermal dielectric layer on the substrate surface back-side of the GaN epi-layer stack and the one or more back-side field plates, the composite thermal dielectric layer comprising a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprisin g one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C) and wherein the composite thermal dielectric layer has a dielectric strength of at least 40V/m and a thermal conductivity of about 2W/m.K or more, such that a thickness of 10pm to 50 m provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
canceled
canceled
The device structure of claim 10 claim 1, wherein the conductive layer on formed on the composite thermal dielectric layer defining the one or more back-side field plates comprises a metal filled thermoplastic polyimide material.
canceled
canceled
(New-Withdrawn) A nitride semiconductor device structure comprising: a GaN epi-layer stack sandwiched between an overlying dielectric support substrate and an underlying, relatively thin dielectric thermal layer; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active region for a lateral GaN transistor and one or more underlying intermediate layers or buffer layers; at least one layer of on-chip metallization provided on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the plurality of lateral GaN transistors, a gate electrode formed on a channel region between the source and drain electrodes, and external contact pads for the source, drain and gate electrodes; the overlying support substrate comprising a layer of a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack, and the support substrate comprising a layer of conductive metallization defining conductive tracks for source, drain and gate interconnections; the external source, drain and gate pads of the lateral GaN transistor being mechanically and electrically interconnected by low inductance interconnections to corresponding source, drain and gate contact areas of 7 said conductive tracks of the overlying support substrate, and dielectric underfill filling gaps between said low inductance interconnections; a conductive layer formed on a back-side of the GaN the epi-layer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; a thermal dielectric layer applied on the back-side of the GaN epi-layer stack and the back-side field plates, the thermal dielectric layer comprising a material having a high thermal conductivity, a CTE closely matched to CTE of the GaN epi-layer stack, and a dielectric strength of at least 4 0V/p m, whereby a layer thickness of the thermal dielectric layer having a thickness of approximately 50 p m provides a breakdown voltage of at least 1000V. withdrawn
(New- withdrawn) A nitride semiconductor device structure of claim 23 wherein the thermal dielectric layer comprises a layer of aluminum nitride or a layer of boron nitride. 8 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN transistor (GaN HEMT) with back-side field plates and composite thermal dielectric
Materials described outside the worked examples.
GaN epi-layer stack
GaN/AlGaN hetero-layer structure
polyimide or epoxy (high dielectric strength polymer dielectric)
composite thermal dielectric layer
Boron Nitride
BN
Aluminum Nitride
AlN
Silicon Nitride
Si₃N₄
thermoplastic polyimide (TPI)
diamond
C
metal filled thermoplastic polyimide
silicon substrate (growth substrate)
Si
ceramic dielectric support layer (header)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
composite thermal dielectric minimum dielectric strength (claim 1) | 40 V/um | composite thermal dielectric layer |
composite thermal dielectric minimum thermal conductivity (claim 1) | 2 W/m.K | composite thermal dielectric layer |
composite thermal dielectric minimum breakdown voltage (claim 1) | 850 V | composite thermal dielectric layer |
composite thermal dielectric maximum thermal resistance (claim 1) | 1 C/W | composite thermal dielectric layer |
composite thermal dielectric minimum dielectric strength (claim 4) | 100 V/um | composite thermal dielectric layer |
composite thermal dielectric thermal conductivity range (claim 4) | 2–5 W/m.K | composite thermal dielectric layer |
composite thermal dielectric breakdown voltage range (claim 4) | 850–2000 V | composite thermal dielectric layer |
— | 2–5 W | — |
Temperature | 200–300 °C | — |
Thickness | 10–50 µm | — |
— | 1.8–2.5 W | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1 V | — |
Temperature | ≤ 1 °C | — |
Voltage | ≥ 40 V | — |
Voltage | ≥ 850 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a GaN die comprising a lateral GaN transistor, the GaN die being sandwiched between an overlying header and an underlying composite thermal dielectric layer; the GaN die comprising: a conductive metallization layer formed thereon one of more layers of on-chip metallization being provided on a front side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front side of the epi layer stack; and overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front side of the GaN die; the overlying header comprising: a support layer substrate comprising a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack and a conductive metallization layer formed on the support layer substrate defining conductive tracks for source, drain and gate interconnections; the overlying header being attached to the GaN die by low inductance conductive interconnections between contact areas of said conductive tracks and respective the contact pads of the source, drain and gate pads electrodes of the lateral GaN transistor and corresponding source, drain and gate contact areas of the conductive tracks of the overlying header; and a conductive layer provided on a back-side of the GaN-epilayer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 2 the composite thermal dielectric layer comprising: a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprising one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride, Aluminum Nitride, Silicon Nitride, diamond, and mixtures thereof, the composite thermal dielectric layer forming a coating on [[a]] the back-side of the G aN epi-layer stack and the one or more back-side field plates, and wherein the composite thermal dielectric has a dielectric strength of at least 40V/pm and a thermal conductivity of about 2W/m.K or more, and the composite thermal dielectric layer has a thickness that provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting of a micro- particulate form of Boron Nitride, Aluminum Nitride, Silicon Nitride, and diamond, and said micro-particulate form comprising micro-particles, micro-flakes, micro-platelets, micro-fibers, nano- particles, nano-platelets, nano-tubes, nano-fibers, and mixtures thereof.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting: Boron Nitride Nano-Tubes (BNNT); Cubic boron nitride powder (c-BN), Boron Nitride nano-particles; hexagonal Boron Nitride flakes (h-BN); and mixtures thereof.
The device of claim 1, wherein the composite thermal dielectric has a dielectric strength of at least 100 V/pm and a thermal conductivity in the range from about 2 W/m.K to 5 W/m.K, and the composite thermal dielectric layer has a thickness in the range from 10 p m to 50 p m and is characterized by a breakdown strength which provides a breakdown voltage in the range from 850V to 2000V and a thermal resistance of less than 1 0 C/W.
The device structure of claim 1, wherein the composite thermal dielectric layer comprises one or more spin-coated layers.
The device structure of claim 1, further comprising a heatspreader layer of a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C), the heatspreader layer being bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising a heatspreader comprising a thermally conductive layer of a ceramic, a metal or a metal alloy, the heatspreader being adhesively bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising external front-side source, drain and gate contact pads for each of the source, drain and gate interconnections provided on an external surface of the support layer substrate of the header, and low inductance conductive vias extending through the support layer substrate from said external front-side source, drain and gate contact areas pads to the 4 respective source, drain and gate contact areas of the conductive metallization layer formed on the support layer substrate of the header.
(Withdrawn-Currently Amended) A method of fabricating the nitride semiconductor device of claim 1, comprising: providing a GaN die comprising a silicon growth substrate having formed thereon a GaN epi-layer stack; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active layer for a lateral GaN transistor and at least one underlying layer comprising a buffer layer or an intermediate layer; [[a]] providing on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, one or more layers of on-chip metallization layer formed on the GaN epi layer stack defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front face of the epi layer stack and the GaN die comprising overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front face of the GaN die, providing a header comprising a support layer substrate of dielectric material having a CTE closely matched to the CTE of the GaN epi-layer stack, and a conductive metallization layer formed on the support layer substrate defining conductive tracks and contact areas for source, drain and gate interconnections, said contact areas for source, drain and gate interconnections having an arrangement for alignment and interconnection with respective the source, drain and gate pads of the GaN die; aligning and assembling the GaN die and the header by providing low inductance conductive interconnections mechanically and electrically interconnecting the source, drain and gate pads of the GaN die with the corresponding source, drain and gate contact areas of conductive tracks of the header; removing the growth substrate from the backside of the epi-layer stack to expose a substrate surface back- side of the GaN epi-layer stack comprising an underlying buffer layer or intermediate layer of the GaN epi-layer stack, the GaN die then being supported by the header; and providing a conductive layer on the back-side of the GaN epi-layer stack, said conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 5 applying a composite thermal dielectric layer on the substrate surface back-side of the GaN epi-layer stack and the one or more back-side field plates, the composite thermal dielectric layer comprising a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprisin g one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C) and wherein the composite thermal dielectric layer has a dielectric strength of at least 40V/m and a thermal conductivity of about 2W/m.K or more, such that a thickness of 10pm to 50 m provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
canceled
canceled
The device structure of claim 10 claim 1, wherein the conductive layer on formed on the composite thermal dielectric layer defining the one or more back-side field plates comprises a metal filled thermoplastic polyimide material.
canceled
canceled
(New-Withdrawn) A nitride semiconductor device structure comprising: a GaN epi-layer stack sandwiched between an overlying dielectric support substrate and an underlying, relatively thin dielectric thermal layer; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active region for a lateral GaN transistor and one or more underlying intermediate layers or buffer layers; at least one layer of on-chip metallization provided on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the plurality of lateral GaN transistors, a gate electrode formed on a channel region between the source and drain electrodes, and external contact pads for the source, drain and gate electrodes; the overlying support substrate comprising a layer of a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack, and the support substrate comprising a layer of conductive metallization defining conductive tracks for source, drain and gate interconnections; the external source, drain and gate pads of the lateral GaN transistor being mechanically and electrically interconnected by low inductance interconnections to corresponding source, drain and gate contact areas of 7 said conductive tracks of the overlying support substrate, and dielectric underfill filling gaps between said low inductance interconnections; a conductive layer formed on a back-side of the GaN the epi-layer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; a thermal dielectric layer applied on the back-side of the GaN epi-layer stack and the back-side field plates, the thermal dielectric layer comprising a material having a high thermal conductivity, a CTE closely matched to CTE of the GaN epi-layer stack, and a dielectric strength of at least 4 0V/p m, whereby a layer thickness of the thermal dielectric layer having a thickness of approximately 50 p m provides a breakdown voltage of at least 1000V. withdrawn
(New- withdrawn) A nitride semiconductor device structure of claim 23 wherein the thermal dielectric layer comprises a layer of aluminum nitride or a layer of boron nitride. 8 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN transistor (GaN HEMT) with back-side field plates and composite thermal dielectric
Materials described outside the worked examples.
GaN epi-layer stack
GaN/AlGaN hetero-layer structure
polyimide or epoxy (high dielectric strength polymer dielectric)
composite thermal dielectric layer
Boron Nitride
BN
Aluminum Nitride
AlN
Silicon Nitride
Si₃N₄
thermoplastic polyimide (TPI)
diamond
C
metal filled thermoplastic polyimide
silicon substrate (growth substrate)
Si
ceramic dielectric support layer (header)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
composite thermal dielectric minimum dielectric strength (claim 1) | 40 V/um | composite thermal dielectric layer |
composite thermal dielectric minimum thermal conductivity (claim 1) | 2 W/m.K | composite thermal dielectric layer |
composite thermal dielectric minimum breakdown voltage (claim 1) | 850 V | composite thermal dielectric layer |
composite thermal dielectric maximum thermal resistance (claim 1) | 1 C/W | composite thermal dielectric layer |
composite thermal dielectric minimum dielectric strength (claim 4) | 100 V/um | composite thermal dielectric layer |
composite thermal dielectric thermal conductivity range (claim 4) | 2–5 W/m.K | composite thermal dielectric layer |
composite thermal dielectric breakdown voltage range (claim 4) | 850–2000 V | composite thermal dielectric layer |
— | 2–5 W | — |
Temperature | 200–300 °C | — |
Thickness | 10–50 µm | — |
— | 1.8–2.5 W | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1 V | — |
Temperature | ≤ 1 °C | — |
Voltage | ≥ 40 V | — |
Voltage | ≥ 850 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a GaN die comprising a lateral GaN transistor, the GaN die being sandwiched between an overlying header and an underlying composite thermal dielectric layer; the GaN die comprising: a conductive metallization layer formed thereon one of more layers of on-chip metallization being provided on a front side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front side of the epi layer stack; and overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front side of the GaN die; the overlying header comprising: a support layer substrate comprising a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack and a conductive metallization layer formed on the support layer substrate defining conductive tracks for source, drain and gate interconnections; the overlying header being attached to the GaN die by low inductance conductive interconnections between contact areas of said conductive tracks and respective the contact pads of the source, drain and gate pads electrodes of the lateral GaN transistor and corresponding source, drain and gate contact areas of the conductive tracks of the overlying header; and a conductive layer provided on a back-side of the GaN-epilayer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 2 the composite thermal dielectric layer comprising: a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprising one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride, Aluminum Nitride, Silicon Nitride, diamond, and mixtures thereof, the composite thermal dielectric layer forming a coating on [[a]] the back-side of the G aN epi-layer stack and the one or more back-side field plates, and wherein the composite thermal dielectric has a dielectric strength of at least 40V/pm and a thermal conductivity of about 2W/m.K or more, and the composite thermal dielectric layer has a thickness that provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting of a micro- particulate form of Boron Nitride, Aluminum Nitride, Silicon Nitride, and diamond, and said micro-particulate form comprising micro-particles, micro-flakes, micro-platelets, micro-fibers, nano- particles, nano-platelets, nano-tubes, nano-fibers, and mixtures thereof.
The device of claim 1, wherein: when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TP I) and the dielectric filler is selected from the group consisting: Boron Nitride Nano-Tubes (BNNT); Cubic boron nitride powder (c-BN), Boron Nitride nano-particles; hexagonal Boron Nitride flakes (h-BN); and mixtures thereof.
The device of claim 1, wherein the composite thermal dielectric has a dielectric strength of at least 100 V/pm and a thermal conductivity in the range from about 2 W/m.K to 5 W/m.K, and the composite thermal dielectric layer has a thickness in the range from 10 p m to 50 p m and is characterized by a breakdown strength which provides a breakdown voltage in the range from 850V to 2000V and a thermal resistance of less than 1 0 C/W.
The device structure of claim 1, wherein the composite thermal dielectric layer comprises one or more spin-coated layers.
The device structure of claim 1, further comprising a heatspreader layer of a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C), the heatspreader layer being bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising a heatspreader comprising a thermally conductive layer of a ceramic, a metal or a metal alloy, the heatspreader being adhesively bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.
The device structure of claim 1, further comprising external front-side source, drain and gate contact pads for each of the source, drain and gate interconnections provided on an external surface of the support layer substrate of the header, and low inductance conductive vias extending through the support layer substrate from said external front-side source, drain and gate contact areas pads to the 4 respective source, drain and gate contact areas of the conductive metallization layer formed on the support layer substrate of the header.
(Withdrawn-Currently Amended) A method of fabricating the nitride semiconductor device of claim 1, comprising: providing a GaN die comprising a silicon growth substrate having formed thereon a GaN epi-layer stack; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active layer for a lateral GaN transistor and at least one underlying layer comprising a buffer layer or an intermediate layer; [[a]] providing on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, one or more layers of on-chip metallization layer formed on the GaN epi layer stack defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes being provided on a front face of the epi layer stack and the GaN die comprising overlying source, drain and gate contact areas (pads) for the lateral GaN transistor on a respective front face of the GaN die, providing a header comprising a support layer substrate of dielectric material having a CTE closely matched to the CTE of the GaN epi-layer stack, and a conductive metallization layer formed on the support layer substrate defining conductive tracks and contact areas for source, drain and gate interconnections, said contact areas for source, drain and gate interconnections having an arrangement for alignment and interconnection with respective the source, drain and gate pads of the GaN die; aligning and assembling the GaN die and the header by providing low inductance conductive interconnections mechanically and electrically interconnecting the source, drain and gate pads of the GaN die with the corresponding source, drain and gate contact areas of conductive tracks of the header; removing the growth substrate from the backside of the epi-layer stack to expose a substrate surface back- side of the GaN epi-layer stack comprising an underlying buffer layer or intermediate layer of the GaN epi-layer stack, the GaN die then being supported by the header; and providing a conductive layer on the back-side of the GaN epi-layer stack, said conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; 5 applying a composite thermal dielectric layer on the substrate surface back-side of the GaN epi-layer stack and the one or more back-side field plates, the composite thermal dielectric layer comprising a high dielectric strength polymer dielectric and a dielectric filler, the high dielectric strength polymer dielectric comprisin g one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (A l N), Silicon Nitride (Si 3 N 4), and diamond (C) and wherein the composite thermal dielectric layer has a dielectric strength of at least 40V/m and a thermal conductivity of about 2W/m.K or more, such that a thickness of 10pm to 50 m provides a breakdown voltage of at least 850V and a thermal resistance of less than 1 0 C/W.
canceled
canceled
The device structure of claim 10 claim 1, wherein the conductive layer on formed on the composite thermal dielectric layer defining the one or more back-side field plates comprises a metal filled thermoplastic polyimide material.
canceled
canceled
(New-Withdrawn) A nitride semiconductor device structure comprising: a GaN epi-layer stack sandwiched between an overlying dielectric support substrate and an underlying, relatively thin dielectric thermal layer; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active region for a lateral GaN transistor and one or more underlying intermediate layers or buffer layers; at least one layer of on-chip metallization provided on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the plurality of lateral GaN transistors, a gate electrode formed on a channel region between the source and drain electrodes, and external contact pads for the source, drain and gate electrodes; the overlying support substrate comprising a layer of a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack, and the support substrate comprising a layer of conductive metallization defining conductive tracks for source, drain and gate interconnections; the external source, drain and gate pads of the lateral GaN transistor being mechanically and electrically interconnected by low inductance interconnections to corresponding source, drain and gate contact areas of 7 said conductive tracks of the overlying support substrate, and dielectric underfill filling gaps between said low inductance interconnections; a conductive layer formed on a back-side of the GaN the epi-layer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor; a thermal dielectric layer applied on the back-side of the GaN epi-layer stack and the back-side field plates, the thermal dielectric layer comprising a material having a high thermal conductivity, a CTE closely matched to CTE of the GaN epi-layer stack, and a dielectric strength of at least 4 0V/p m, whereby a layer thickness of the thermal dielectric layer having a thickness of approximately 50 p m provides a breakdown voltage of at least 1000V. withdrawn
(New- withdrawn) A nitride semiconductor device structure of claim 23 wherein the thermal dielectric layer comprises a layer of aluminum nitride or a layer of boron nitride. 8 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN transistor (GaN HEMT) with back-side field plates and composite thermal dielectric
Materials described outside the worked examples.
GaN epi-layer stack
GaN/AlGaN hetero-layer structure
polyimide or epoxy (high dielectric strength polymer dielectric)
composite thermal dielectric layer
Boron Nitride
BN
Aluminum Nitride
AlN
Silicon Nitride
Si₃N₄
thermoplastic polyimide (TPI)
diamond
C
metal filled thermoplastic polyimide
silicon substrate (growth substrate)
Si
ceramic dielectric support layer (header)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
composite thermal dielectric minimum dielectric strength (claim 1) | 40 V/um | composite thermal dielectric layer |
composite thermal dielectric minimum thermal conductivity (claim 1) | 2 W/m.K | composite thermal dielectric layer |
composite thermal dielectric minimum breakdown voltage (claim 1) | 850 V | composite thermal dielectric layer |
composite thermal dielectric maximum thermal resistance (claim 1) | 1 C/W | composite thermal dielectric layer |
composite thermal dielectric minimum dielectric strength (claim 4) | 100 V/um | composite thermal dielectric layer |
composite thermal dielectric thermal conductivity range (claim 4) | 2–5 W/m.K | composite thermal dielectric layer |
composite thermal dielectric breakdown voltage range (claim 4) | 850–2000 V | composite thermal dielectric layer |
— | 2–5 W | — |
Temperature | 200–300 °C | — |
Thickness | 10–50 µm | — |
— | 1.8–2.5 W | — |
Voltage | ≥ 1200 V | — |
Voltage | ≥ 1 V | — |
Temperature | ≤ 1 °C | — |
Voltage | ≥ 40 V | — |
Voltage | ≥ 850 V | — |