Patent
US 8,530,886NITRIDE GATE DIELECTRIC FOR GRAPHENE MOSFET
Phaedon Avouris
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,530,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view of a first exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 2 is a process flow for forming the first exemplary embodiment in
Figure 3 is a cross sectional view of a second exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 4 is a process flow for forming the second exemplary embodiment in
Figure 5 is a cross sectional view of a third exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 6 is a process flow for forming the third exemplary embodiment in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode.
A semiconductor structure com p risin q: a substrate; a qrap hene layer on the substrate; a source electrode and a drain electrode on the qrap hene layer, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension; a nitride layer on the qrap hene layer between the source electrode and drain electrode; and a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode The semiconductor Gtructure of claiM 1 wherein the nitride layer extends only under the gate electrode.
The semiconductor structure of claim 1 wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode and continues up a sidewall of the source electrode and a sidewall of the drain electrode.
The semiconductor structure of claim 1 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.
The semiconductor structure of claim 1 wherein the substrate is selected from the group consisting of a semiconductor substrate, an insulator substrate, a polymer substrate, a layered substrate and combinations of any of the foregoing substrates.
The semiconductor structure of claim 1 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
The method of claim 1-5 16 wherein the qrap hene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
Canceled.
The semiconductor structure of claim [[2]].1 further comprising a spacer adjacent the gate electrode and on the nitride layer.
The semiconductor structure of claim [[1]] 4 wherein the qrap hene la y er is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
YO R₉₂₀₁₀₀₄₇₅US₁ -3- 13/051,707 15. A method of forming a semiconductor structure comprising: providing a substrate; forming a graphene layer on the substrate; depositing a nitride layer on the graphene layer; forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending the entireat l east part of the predetermined dimension between the source electrode and drain electrode; and forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
A method of formin q a semiconductor structure com p risin q: p rovidin q a substrate: formin q a qrap hene layer on the substrate; dep ositin q a nitride layer on the qrap hene layer; formin q a source electrode and a drain electrode on the qrap hene la v er, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension, the nitride layer extend inq at least part of the predetermined dimension between the source electrode and drain electrode; and formin q a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode and The method of claim 15 further comprising patterning the nitride layer so as to remove the nitride layer from portions of the graphene layer.
YOR₉ 20100475 US 1 -4- 13/051,707 19. The method of claim 15 further comprising forming a spacer adjacent the gate electrode and on the nitride layer.
The method of claim 15 wherein forming a source electrode and a drain electrode occurs prior to depositing a nitride layer and wherein depositing a nitride layer includes depositing the nitride layer on a sidewall of the source electrode and a sidewall of the drain electrode.
The method of claim 15 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.
The method of claim 15 wherein the wherein the step of forming is carried out using a preformed graphene.
The method of claim 15 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
Canceled.
Layer stacks claimed or described, ordered top of device to substrate.
graphene MOSFET
Materials described outside the worked examples.
graphene
C
nitride layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nitride film thickness | 2–20 nm | nitride layer |
Duration | 10–60 seconds |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view of a first exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 2 is a process flow for forming the first exemplary embodiment in
Figure 3 is a cross sectional view of a second exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 4 is a process flow for forming the second exemplary embodiment in
Figure 5 is a cross sectional view of a third exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 6 is a process flow for forming the third exemplary embodiment in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode.
A semiconductor structure com p risin q: a substrate; a qrap hene layer on the substrate; a source electrode and a drain electrode on the qrap hene layer, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension; a nitride layer on the qrap hene layer between the source electrode and drain electrode; and a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode The semiconductor Gtructure of claiM 1 wherein the nitride layer extends only under the gate electrode.
The semiconductor structure of claim 1 wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode and continues up a sidewall of the source electrode and a sidewall of the drain electrode.
The semiconductor structure of claim 1 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.
The semiconductor structure of claim 1 wherein the substrate is selected from the group consisting of a semiconductor substrate, an insulator substrate, a polymer substrate, a layered substrate and combinations of any of the foregoing substrates.
The semiconductor structure of claim 1 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
The method of claim 1-5 16 wherein the qrap hene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
Canceled.
The semiconductor structure of claim [[2]].1 further comprising a spacer adjacent the gate electrode and on the nitride layer.
The semiconductor structure of claim [[1]] 4 wherein the qrap hene la y er is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
YO R₉₂₀₁₀₀₄₇₅US₁ -3- 13/051,707 15. A method of forming a semiconductor structure comprising: providing a substrate; forming a graphene layer on the substrate; depositing a nitride layer on the graphene layer; forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending the entireat l east part of the predetermined dimension between the source electrode and drain electrode; and forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
A method of formin q a semiconductor structure com p risin q: p rovidin q a substrate: formin q a qrap hene layer on the substrate; dep ositin q a nitride layer on the qrap hene layer; formin q a source electrode and a drain electrode on the qrap hene la v er, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension, the nitride layer extend inq at least part of the predetermined dimension between the source electrode and drain electrode; and formin q a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode and The method of claim 15 further comprising patterning the nitride layer so as to remove the nitride layer from portions of the graphene layer.
YOR₉ 20100475 US 1 -4- 13/051,707 19. The method of claim 15 further comprising forming a spacer adjacent the gate electrode and on the nitride layer.
The method of claim 15 wherein forming a source electrode and a drain electrode occurs prior to depositing a nitride layer and wherein depositing a nitride layer includes depositing the nitride layer on a sidewall of the source electrode and a sidewall of the drain electrode.
The method of claim 15 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.
The method of claim 15 wherein the wherein the step of forming is carried out using a preformed graphene.
The method of claim 15 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
Canceled.
Layer stacks claimed or described, ordered top of device to substrate.
graphene MOSFET
Materials described outside the worked examples.
graphene
C
nitride layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nitride film thickness | 2–20 nm | nitride layer |
Duration | 10–60 seconds |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view of a first exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 2 is a process flow for forming the first exemplary embodiment in
Figure 3 is a cross sectional view of a second exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 4 is a process flow for forming the second exemplary embodiment in
Figure 5 is a cross sectional view of a third exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 6 is a process flow for forming the third exemplary embodiment in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode.
A semiconductor structure com p risin q: a substrate; a qrap hene layer on the substrate; a source electrode and a drain electrode on the qrap hene layer, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension; a nitride layer on the qrap hene layer between the source electrode and drain electrode; and a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode The semiconductor Gtructure of claiM 1 wherein the nitride layer extends only under the gate electrode.
The semiconductor structure of claim 1 wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode and continues up a sidewall of the source electrode and a sidewall of the drain electrode.
The semiconductor structure of claim 1 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.
The semiconductor structure of claim 1 wherein the substrate is selected from the group consisting of a semiconductor substrate, an insulator substrate, a polymer substrate, a layered substrate and combinations of any of the foregoing substrates.
The semiconductor structure of claim 1 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
The method of claim 1-5 16 wherein the qrap hene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
Canceled.
The semiconductor structure of claim [[2]].1 further comprising a spacer adjacent the gate electrode and on the nitride layer.
The semiconductor structure of claim [[1]] 4 wherein the qrap hene la y er is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
YO R₉₂₀₁₀₀₄₇₅US₁ -3- 13/051,707 15. A method of forming a semiconductor structure comprising: providing a substrate; forming a graphene layer on the substrate; depositing a nitride layer on the graphene layer; forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending the entireat l east part of the predetermined dimension between the source electrode and drain electrode; and forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
A method of formin q a semiconductor structure com p risin q: p rovidin q a substrate: formin q a qrap hene layer on the substrate; dep ositin q a nitride layer on the qrap hene layer; formin q a source electrode and a drain electrode on the qrap hene la v er, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension, the nitride layer extend inq at least part of the predetermined dimension between the source electrode and drain electrode; and formin q a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode and The method of claim 15 further comprising patterning the nitride layer so as to remove the nitride layer from portions of the graphene layer.
YOR₉ 20100475 US 1 -4- 13/051,707 19. The method of claim 15 further comprising forming a spacer adjacent the gate electrode and on the nitride layer.
The method of claim 15 wherein forming a source electrode and a drain electrode occurs prior to depositing a nitride layer and wherein depositing a nitride layer includes depositing the nitride layer on a sidewall of the source electrode and a sidewall of the drain electrode.
The method of claim 15 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.
The method of claim 15 wherein the wherein the step of forming is carried out using a preformed graphene.
The method of claim 15 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
Canceled.
Layer stacks claimed or described, ordered top of device to substrate.
graphene MOSFET
Materials described outside the worked examples.
graphene
C
nitride layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nitride film thickness | 2–20 nm | nitride layer |
Duration | 10–60 seconds |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view of a first exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 2 is a process flow for forming the first exemplary embodiment in
Figure 3 is a cross sectional view of a second exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 4 is a process flow for forming the second exemplary embodiment in
Figure 5 is a cross sectional view of a third exemplary embodiment of a semiconductor structure having a graphene layer on a substrate.
Figure 6 is a process flow for forming the third exemplary embodiment in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode.
A semiconductor structure com p risin q: a substrate; a qrap hene layer on the substrate; a source electrode and a drain electrode on the qrap hene layer, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension; a nitride layer on the qrap hene layer between the source electrode and drain electrode; and a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode The semiconductor Gtructure of claiM 1 wherein the nitride layer extends only under the gate electrode.
The semiconductor structure of claim 1 wherein the nitride layer extends the entire predetermined dimension between the source electrode and the drain electrode and continues up a sidewall of the source electrode and a sidewall of the drain electrode.
The semiconductor structure of claim 1 wherein the nitride layer can be aluminum nitride, silicon nitride, hafnium nitride or zirconium nitride.
The semiconductor structure of claim 1 wherein the substrate is selected from the group consisting of a semiconductor substrate, an insulator substrate, a polymer substrate, a layered substrate and combinations of any of the foregoing substrates.
The semiconductor structure of claim 1 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
The method of claim 1-5 16 wherein the qrap hene layer is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
Canceled.
The semiconductor structure of claim [[2]].1 further comprising a spacer adjacent the gate electrode and on the nitride layer.
The semiconductor structure of claim [[1]] 4 wherein the qrap hene la y er is in direct contact with the substrate and the nitride layer is in direct contact with the graphene layer.
YO R₉₂₀₁₀₀₄₇₅US₁ -3- 13/051,707 15. A method of forming a semiconductor structure comprising: providing a substrate; forming a graphene layer on the substrate; depositing a nitride layer on the graphene layer; forming a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension, the nitride layer extending the entireat l east part of the predetermined dimension between the source electrode and drain electrode; and forming a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
A method of formin q a semiconductor structure com p risin q: p rovidin q a substrate: formin q a qrap hene layer on the substrate; dep ositin q a nitride layer on the qrap hene layer; formin q a source electrode and a drain electrode on the qrap hene la v er, the source electrode and drain electrode bein q sp aced a p art by a p redetermined dimension, the nitride layer extend inq at least part of the predetermined dimension between the source electrode and drain electrode; and formin q a q ate electrode on the nitride layer, wherein the nitride layer is a q ate dielectric for the q ate electrode and The method of claim 15 further comprising patterning the nitride layer so as to remove the nitride layer from portions of the graphene layer.
YOR₉ 20100475 US 1 -4- 13/051,707 19. The method of claim 15 further comprising forming a spacer adjacent the gate electrode and on the nitride layer.
The method of claim 15 wherein forming a source electrode and a drain electrode occurs prior to depositing a nitride layer and wherein depositing a nitride layer includes depositing the nitride layer on a sidewall of the source electrode and a sidewall of the drain electrode.
The method of claim 15 wherein the nitride layer is selected from the group consisting of aluminum nitride, silicon nitride, hafnium nitride and zirconium nitride.
The method of claim 15 wherein the wherein the step of forming is carried out using a preformed graphene.
The method of claim 15 wherein the graphene layer is in direct contact with the substrate and the nitride layer is in direct contact with the qrap hene layer.
Canceled.
Layer stacks claimed or described, ordered top of device to substrate.
graphene MOSFET
Materials described outside the worked examples.
graphene
C
nitride layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nitride film thickness | 2–20 nm | nitride layer |
Duration | 10–60 seconds |
Related documents with shared materials, methods, properties, or citations.
aluminum nitride
AlN
silicon nitride
Si₃N₄
hafnium nitride
HfN
zirconium nitride
ZrN
| — |
Duration | 10–60 minutes | — |
aluminum nitride
AlN
silicon nitride
Si₃N₄
hafnium nitride
HfN
zirconium nitride
ZrN
| — |
Duration | 10–60 minutes | — |
aluminum nitride
AlN
silicon nitride
Si₃N₄
hafnium nitride
HfN
zirconium nitride
ZrN
| — |
Duration | 10–60 minutes | — |
aluminum nitride
AlN
silicon nitride
Si₃N₄
hafnium nitride
HfN
zirconium nitride
ZrN
| — |
Duration | 10–60 minutes | — |