Patent
US 11,201,260Semiconductor Chip of Light Emitting Diode and Quantum Well Layer Thereof
Zhi WAN
US
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Patent
Atlas literature
Patent
US 11,201,260Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor chip of a light emitting diode, comprising: a substrate; an N-type gallium nitride layer, which is stacked on said substrate; a quantum well layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer comprises one or more quantum barriers and one or more quantum wells stacked successively in sequence, wherein a growth pressure of said one or more quantum barriers and a growth pressure of said one or more quantum wells are different; a P-type gallium nitride layer, wherein said P-type gallium nitride layer is stacked on said quantum well layer; an N-type electrode, electrically connected to said N-type gallium nitride layer; a P-type electrode, electrically connected to said P-type gallium nitride layer; and a current spreadin g la y er stacked on and electrically connected to said N-type q allium nitride la y er, wherein said q uantum well la y er is stacked on said current spreadin g la y er while said N-type electrode is stacked on and electrically connected to said current spreadin g la y er, such that said N-type q allium nitride la y er is electrically connected to said N-type electrode via said current spreadin g la y er for a current from said N-type electrode capable of enterin q to said q uantum well la y er throu q h said N-type q allium nitride la y er. Currently amended
The semiconductor chip, as recited in claim 1, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells of said quantum well layer. Original
The semiconductor chip, as recited in claim 1, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Alx 1lny1Ga₁-x1-y1 N (0 <X1<1, 0 <Y1<1), having a doped concentration of 1- 5x101 8cm⁻³, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Alx2 l ny2Ga 1 -x2-y2N (0<X 2<1, 0 <Y2<1). Original
The semiconductor chip, as recited in claim 1, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer. Original
The semiconductor chip, as recited in claim 1, wherein said current spreadin g la y er is one of an N-type current spreadin g la y er, an AIGaN current spreadin g la y er, and an InGaN current spreadin g la y er. Currently amended
The semiconductor chip, as recited in claim 1, further comprising a protective layer stacked on said quantum well layer to maintain crystal quality thereof, wherein said P-type gallium nitride layer is stacked on said protective layer. Currently amended
The semiconductor chip, as recited in claim 40 2, wherein said current spreading layer is one of an N-type current spreading layer, an AIGaN current spreading layer, and an InGaN current spreading layer. Currently amended
A manufacturing method of a semiconductor chip of a light emitting diode, comprising the steps of: (a) stacking an N-type gallium nitride layer on a substrate; (b) cyclically growing one or more quantum barriers and one or more quantum wells from said N-type gallium nitride layer to form a quantum well layer, wherein said one or more quantum barriers and said one or more quantum wells are stacked successively in sequence on said N-type gallium nitride layer, wherein a growth pressure of said quantum barrier and a growth pressure of said quantum well are different; (c) stacking a P-type gallium nitride layer on said quantum well layer; and (d) electrically connecting an N-type electrode to said N-type gallium nitride layer and electrically connecting a P-type electrode to said P-type gallium nitride layer. Withdrawn
The manufacturing method, as recited in claim 20, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells. Withdrawn
The manufacturing method, as recited in claim 20, before the step (a), further comprising a step of growing a buffer layer from said substrate, so that in the step (a), said N-type nitrogen gallium layer is grown on said buffer layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (b), further comprising a step of growing a current spreading layer from said N- type gallium nitride layer, so that in the step (b), said quantum well layer is grown on said current spreading layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (c), further comprising the steps of growing a protective layer from said quantum well layer and growing an electron blocking layer from said protective layer, so that in the step (c), said P-type gallium nitride layer is grown on said electron blocking layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
LED semiconductor chip
Materials described outside the worked examples.
N-type gallium nitride layer
GaN
quantum well layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
quantum barrier thickness | 5–15 nm | Alx1Iny1Ga₁-x1-y1N |
quantum well thickness | 2–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,201,260Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor chip of a light emitting diode, comprising: a substrate; an N-type gallium nitride layer, which is stacked on said substrate; a quantum well layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer comprises one or more quantum barriers and one or more quantum wells stacked successively in sequence, wherein a growth pressure of said one or more quantum barriers and a growth pressure of said one or more quantum wells are different; a P-type gallium nitride layer, wherein said P-type gallium nitride layer is stacked on said quantum well layer; an N-type electrode, electrically connected to said N-type gallium nitride layer; a P-type electrode, electrically connected to said P-type gallium nitride layer; and a current spreadin g la y er stacked on and electrically connected to said N-type q allium nitride la y er, wherein said q uantum well la y er is stacked on said current spreadin g la y er while said N-type electrode is stacked on and electrically connected to said current spreadin g la y er, such that said N-type q allium nitride la y er is electrically connected to said N-type electrode via said current spreadin g la y er for a current from said N-type electrode capable of enterin q to said q uantum well la y er throu q h said N-type q allium nitride la y er. Currently amended
The semiconductor chip, as recited in claim 1, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells of said quantum well layer. Original
The semiconductor chip, as recited in claim 1, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Alx 1lny1Ga₁-x1-y1 N (0 <X1<1, 0 <Y1<1), having a doped concentration of 1- 5x101 8cm⁻³, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Alx2 l ny2Ga 1 -x2-y2N (0<X 2<1, 0 <Y2<1). Original
The semiconductor chip, as recited in claim 1, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer. Original
The semiconductor chip, as recited in claim 1, wherein said current spreadin g la y er is one of an N-type current spreadin g la y er, an AIGaN current spreadin g la y er, and an InGaN current spreadin g la y er. Currently amended
The semiconductor chip, as recited in claim 1, further comprising a protective layer stacked on said quantum well layer to maintain crystal quality thereof, wherein said P-type gallium nitride layer is stacked on said protective layer. Currently amended
The semiconductor chip, as recited in claim 40 2, wherein said current spreading layer is one of an N-type current spreading layer, an AIGaN current spreading layer, and an InGaN current spreading layer. Currently amended
A manufacturing method of a semiconductor chip of a light emitting diode, comprising the steps of: (a) stacking an N-type gallium nitride layer on a substrate; (b) cyclically growing one or more quantum barriers and one or more quantum wells from said N-type gallium nitride layer to form a quantum well layer, wherein said one or more quantum barriers and said one or more quantum wells are stacked successively in sequence on said N-type gallium nitride layer, wherein a growth pressure of said quantum barrier and a growth pressure of said quantum well are different; (c) stacking a P-type gallium nitride layer on said quantum well layer; and (d) electrically connecting an N-type electrode to said N-type gallium nitride layer and electrically connecting a P-type electrode to said P-type gallium nitride layer. Withdrawn
The manufacturing method, as recited in claim 20, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells. Withdrawn
The manufacturing method, as recited in claim 20, before the step (a), further comprising a step of growing a buffer layer from said substrate, so that in the step (a), said N-type nitrogen gallium layer is grown on said buffer layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (b), further comprising a step of growing a current spreading layer from said N- type gallium nitride layer, so that in the step (b), said quantum well layer is grown on said current spreading layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (c), further comprising the steps of growing a protective layer from said quantum well layer and growing an electron blocking layer from said protective layer, so that in the step (c), said P-type gallium nitride layer is grown on said electron blocking layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
LED semiconductor chip
Materials described outside the worked examples.
N-type gallium nitride layer
GaN
quantum well layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
quantum barrier thickness | 5–15 nm | Alx1Iny1Ga₁-x1-y1N |
quantum well thickness | 2–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,201,260Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor chip of a light emitting diode, comprising: a substrate; an N-type gallium nitride layer, which is stacked on said substrate; a quantum well layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer comprises one or more quantum barriers and one or more quantum wells stacked successively in sequence, wherein a growth pressure of said one or more quantum barriers and a growth pressure of said one or more quantum wells are different; a P-type gallium nitride layer, wherein said P-type gallium nitride layer is stacked on said quantum well layer; an N-type electrode, electrically connected to said N-type gallium nitride layer; a P-type electrode, electrically connected to said P-type gallium nitride layer; and a current spreadin g la y er stacked on and electrically connected to said N-type q allium nitride la y er, wherein said q uantum well la y er is stacked on said current spreadin g la y er while said N-type electrode is stacked on and electrically connected to said current spreadin g la y er, such that said N-type q allium nitride la y er is electrically connected to said N-type electrode via said current spreadin g la y er for a current from said N-type electrode capable of enterin q to said q uantum well la y er throu q h said N-type q allium nitride la y er. Currently amended
The semiconductor chip, as recited in claim 1, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells of said quantum well layer. Original
The semiconductor chip, as recited in claim 1, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Alx 1lny1Ga₁-x1-y1 N (0 <X1<1, 0 <Y1<1), having a doped concentration of 1- 5x101 8cm⁻³, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Alx2 l ny2Ga 1 -x2-y2N (0<X 2<1, 0 <Y2<1). Original
The semiconductor chip, as recited in claim 1, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer. Original
The semiconductor chip, as recited in claim 1, wherein said current spreadin g la y er is one of an N-type current spreadin g la y er, an AIGaN current spreadin g la y er, and an InGaN current spreadin g la y er. Currently amended
The semiconductor chip, as recited in claim 1, further comprising a protective layer stacked on said quantum well layer to maintain crystal quality thereof, wherein said P-type gallium nitride layer is stacked on said protective layer. Currently amended
The semiconductor chip, as recited in claim 40 2, wherein said current spreading layer is one of an N-type current spreading layer, an AIGaN current spreading layer, and an InGaN current spreading layer. Currently amended
A manufacturing method of a semiconductor chip of a light emitting diode, comprising the steps of: (a) stacking an N-type gallium nitride layer on a substrate; (b) cyclically growing one or more quantum barriers and one or more quantum wells from said N-type gallium nitride layer to form a quantum well layer, wherein said one or more quantum barriers and said one or more quantum wells are stacked successively in sequence on said N-type gallium nitride layer, wherein a growth pressure of said quantum barrier and a growth pressure of said quantum well are different; (c) stacking a P-type gallium nitride layer on said quantum well layer; and (d) electrically connecting an N-type electrode to said N-type gallium nitride layer and electrically connecting a P-type electrode to said P-type gallium nitride layer. Withdrawn
The manufacturing method, as recited in claim 20, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells. Withdrawn
The manufacturing method, as recited in claim 20, before the step (a), further comprising a step of growing a buffer layer from said substrate, so that in the step (a), said N-type nitrogen gallium layer is grown on said buffer layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (b), further comprising a step of growing a current spreading layer from said N- type gallium nitride layer, so that in the step (b), said quantum well layer is grown on said current spreading layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (c), further comprising the steps of growing a protective layer from said quantum well layer and growing an electron blocking layer from said protective layer, so that in the step (c), said P-type gallium nitride layer is grown on said electron blocking layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
LED semiconductor chip
Materials described outside the worked examples.
N-type gallium nitride layer
GaN
quantum well layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
quantum barrier thickness | 5–15 nm | Alx1Iny1Ga₁-x1-y1N |
quantum well thickness | 2–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,201,260Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor chip of a light emitting diode, comprising: a substrate; an N-type gallium nitride layer, which is stacked on said substrate; a quantum well layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer comprises one or more quantum barriers and one or more quantum wells stacked successively in sequence, wherein a growth pressure of said one or more quantum barriers and a growth pressure of said one or more quantum wells are different; a P-type gallium nitride layer, wherein said P-type gallium nitride layer is stacked on said quantum well layer; an N-type electrode, electrically connected to said N-type gallium nitride layer; a P-type electrode, electrically connected to said P-type gallium nitride layer; and a current spreadin g la y er stacked on and electrically connected to said N-type q allium nitride la y er, wherein said q uantum well la y er is stacked on said current spreadin g la y er while said N-type electrode is stacked on and electrically connected to said current spreadin g la y er, such that said N-type q allium nitride la y er is electrically connected to said N-type electrode via said current spreadin g la y er for a current from said N-type electrode capable of enterin q to said q uantum well la y er throu q h said N-type q allium nitride la y er. Currently amended
The semiconductor chip, as recited in claim 1, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells of said quantum well layer. Original
The semiconductor chip, as recited in claim 1, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Alx 1lny1Ga₁-x1-y1 N (0 <X1<1, 0 <Y1<1), having a doped concentration of 1- 5x101 8cm⁻³, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Alx2 l ny2Ga 1 -x2-y2N (0<X 2<1, 0 <Y2<1). Original
The semiconductor chip, as recited in claim 1, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer. Original
The semiconductor chip, as recited in claim 1, wherein said current spreadin g la y er is one of an N-type current spreadin g la y er, an AIGaN current spreadin g la y er, and an InGaN current spreadin g la y er. Currently amended
The semiconductor chip, as recited in claim 1, further comprising a protective layer stacked on said quantum well layer to maintain crystal quality thereof, wherein said P-type gallium nitride layer is stacked on said protective layer. Currently amended
The semiconductor chip, as recited in claim 40 2, wherein said current spreading layer is one of an N-type current spreading layer, an AIGaN current spreading layer, and an InGaN current spreading layer. Currently amended
A manufacturing method of a semiconductor chip of a light emitting diode, comprising the steps of: (a) stacking an N-type gallium nitride layer on a substrate; (b) cyclically growing one or more quantum barriers and one or more quantum wells from said N-type gallium nitride layer to form a quantum well layer, wherein said one or more quantum barriers and said one or more quantum wells are stacked successively in sequence on said N-type gallium nitride layer, wherein a growth pressure of said quantum barrier and a growth pressure of said quantum well are different; (c) stacking a P-type gallium nitride layer on said quantum well layer; and (d) electrically connecting an N-type electrode to said N-type gallium nitride layer and electrically connecting a P-type electrode to said P-type gallium nitride layer. Withdrawn
The manufacturing method, as recited in claim 20, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells. Withdrawn
The manufacturing method, as recited in claim 20, before the step (a), further comprising a step of growing a buffer layer from said substrate, so that in the step (a), said N-type nitrogen gallium layer is grown on said buffer layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (b), further comprising a step of growing a current spreading layer from said N- type gallium nitride layer, so that in the step (b), said quantum well layer is grown on said current spreading layer. Withdrawn
The manufacturing method, as recited in claim 20, before the step (c), further comprising the steps of growing a protective layer from said quantum well layer and growing an electron blocking layer from said protective layer, so that in the step (c), said P-type gallium nitride layer is grown on said electron blocking layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
LED semiconductor chip
Materials described outside the worked examples.
N-type gallium nitride layer
GaN
quantum well layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
quantum barrier thickness | 5–15 nm | Alx1Iny1Ga₁-x1-y1N |
quantum well thickness | 2–5 nm |
Related documents with shared materials, methods, properties, or citations.
doped quantum barrier
Alx1Iny1Ga₁-x1-y1N
undoped quantum well
Alx2Iny2Ga₁-x2-y2N
buffer layer
AlN buffer layer
AlN
N-type current spreading layer
AlGaN current spreading layer
AlGaN
InGaN current spreading layer
InGaN
quantum barrier doped concentration | 1000000000000000000–5000000000000000000 cm⁻³ | Alx1Iny1Ga₁-x1-y1N |
protective GaN cap layer thickness | 30–100 nm | GaN |
electron blocking layer doped concentration | 1000000000000000000–10000000000000000000 cm⁻³ | AlGaN |
electron blocking layer thickness | 0.1–0.5 um | AlGaN |
Thickness | 0–200 nm | — |
Thickness | 20–50 nm | — |
Duration | 10–15 minutes | — |
Duration | 20–30 minutes | — |
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
doped quantum barrier
Alx1Iny1Ga₁-x1-y1N
undoped quantum well
Alx2Iny2Ga₁-x2-y2N
buffer layer
AlN buffer layer
AlN
N-type current spreading layer
AlGaN current spreading layer
AlGaN
InGaN current spreading layer
InGaN
quantum barrier doped concentration | 1000000000000000000–5000000000000000000 cm⁻³ | Alx1Iny1Ga₁-x1-y1N |
protective GaN cap layer thickness | 30–100 nm | GaN |
electron blocking layer doped concentration | 1000000000000000000–10000000000000000000 cm⁻³ | AlGaN |
electron blocking layer thickness | 0.1–0.5 um | AlGaN |
Thickness | 0–200 nm | — |
Thickness | 20–50 nm | — |
Duration | 10–15 minutes | — |
Duration | 20–30 minutes | — |
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
doped quantum barrier
Alx1Iny1Ga₁-x1-y1N
undoped quantum well
Alx2Iny2Ga₁-x2-y2N
buffer layer
AlN buffer layer
AlN
N-type current spreading layer
AlGaN current spreading layer
AlGaN
InGaN current spreading layer
InGaN
quantum barrier doped concentration | 1000000000000000000–5000000000000000000 cm⁻³ | Alx1Iny1Ga₁-x1-y1N |
protective GaN cap layer thickness | 30–100 nm | GaN |
electron blocking layer doped concentration | 1000000000000000000–10000000000000000000 cm⁻³ | AlGaN |
electron blocking layer thickness | 0.1–0.5 um | AlGaN |
Thickness | 0–200 nm | — |
Thickness | 20–50 nm | — |
Duration | 10–15 minutes | — |
Duration | 20–30 minutes | — |
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
doped quantum barrier
Alx1Iny1Ga₁-x1-y1N
undoped quantum well
Alx2Iny2Ga₁-x2-y2N
buffer layer
AlN buffer layer
AlN
N-type current spreading layer
AlGaN current spreading layer
AlGaN
InGaN current spreading layer
InGaN
quantum barrier doped concentration | 1000000000000000000–5000000000000000000 cm⁻³ | Alx1Iny1Ga₁-x1-y1N |
protective GaN cap layer thickness | 30–100 nm | GaN |
electron blocking layer doped concentration | 1000000000000000000–10000000000000000000 cm⁻³ | AlGaN |
electron blocking layer thickness | 0.1–0.5 um | AlGaN |
Thickness | 0–200 nm | — |
Thickness | 20–50 nm | — |
Duration | 10–15 minutes | — |
Duration | 20–30 minutes | — |