Patent
US 9,602,125WIDEBAND InP DIGITAL-TO-ANALOG CONVERTER INTEGRATED WITH A SiGe CLOCK DISTRIBUTION NETWORK
CHRISTOPHER LANGIT
US
Copyright © 2026 Matter42. All rights reserved.
Patent details
Patent
US 9,602,125Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a high level schematic diagram of a DAC including a DAC core circuit and a clock tree distribution network;
Figure 2 is a schematic diagram of the DAC core circuit shown in figure 1;
Figure 3 is a schematic diagram of a current switching circuit in one of the DAC core circuit cells; and
Figure 4 is a schematic diagram of the clock tree distribution network shown in figure 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits; a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 1 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 1 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 1 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
The DAC according to claim 1 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 1 wherein the DAC circuit receives twelve input bits.
The DAC according to claim 1 wherein the current switches include most significant bit current switches and least significant bit current switches.
The DAC according to claim 1 wherein the converted analog signal represents the digital bit input signals in both frequency and amplitude.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits, where the converted analog signal represents the digital bits in both frequency and amplitude; 8 Docket No. NGC-00160 (006887-0030) a clock circuit responsive to a sinusoidal clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 11 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 11 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a 9 Docket No. NGC-00160 (006887-0030) plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 11 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
A digital-to-analog converter (DAC) comprising a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits and a clock tree distribution network providing a plurality of clock signals to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 17 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 17 wherein the DAC receives a clock input signal at 26 GHz and provides a clock output signal at 13 GHz.
The DAC according to claim 17 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the
Layer stacks claimed or described, ordered top of device to substrate.
wideband InP DAC integrated with SiGe clock distribution network
Materials described outside the worked examples.
indium phosphide
InP
silicon germanium
SiGe
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 9,602,125Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a high level schematic diagram of a DAC including a DAC core circuit and a clock tree distribution network;
Figure 2 is a schematic diagram of the DAC core circuit shown in figure 1;
Figure 3 is a schematic diagram of a current switching circuit in one of the DAC core circuit cells; and
Figure 4 is a schematic diagram of the clock tree distribution network shown in figure 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits; a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 1 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 1 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 1 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
The DAC according to claim 1 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 1 wherein the DAC circuit receives twelve input bits.
The DAC according to claim 1 wherein the current switches include most significant bit current switches and least significant bit current switches.
The DAC according to claim 1 wherein the converted analog signal represents the digital bit input signals in both frequency and amplitude.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits, where the converted analog signal represents the digital bits in both frequency and amplitude; 8 Docket No. NGC-00160 (006887-0030) a clock circuit responsive to a sinusoidal clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 11 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 11 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a 9 Docket No. NGC-00160 (006887-0030) plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 11 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
A digital-to-analog converter (DAC) comprising a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits and a clock tree distribution network providing a plurality of clock signals to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 17 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 17 wherein the DAC receives a clock input signal at 26 GHz and provides a clock output signal at 13 GHz.
The DAC according to claim 17 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the
Layer stacks claimed or described, ordered top of device to substrate.
wideband InP DAC integrated with SiGe clock distribution network
Materials described outside the worked examples.
indium phosphide
InP
silicon germanium
SiGe
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 9,602,125Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a high level schematic diagram of a DAC including a DAC core circuit and a clock tree distribution network;
Figure 2 is a schematic diagram of the DAC core circuit shown in figure 1;
Figure 3 is a schematic diagram of a current switching circuit in one of the DAC core circuit cells; and
Figure 4 is a schematic diagram of the clock tree distribution network shown in figure 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits; a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 1 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 1 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 1 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
The DAC according to claim 1 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 1 wherein the DAC circuit receives twelve input bits.
The DAC according to claim 1 wherein the current switches include most significant bit current switches and least significant bit current switches.
The DAC according to claim 1 wherein the converted analog signal represents the digital bit input signals in both frequency and amplitude.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits, where the converted analog signal represents the digital bits in both frequency and amplitude; 8 Docket No. NGC-00160 (006887-0030) a clock circuit responsive to a sinusoidal clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 11 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 11 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a 9 Docket No. NGC-00160 (006887-0030) plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 11 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
A digital-to-analog converter (DAC) comprising a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits and a clock tree distribution network providing a plurality of clock signals to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 17 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 17 wherein the DAC receives a clock input signal at 26 GHz and provides a clock output signal at 13 GHz.
The DAC according to claim 17 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the
Layer stacks claimed or described, ordered top of device to substrate.
wideband InP DAC integrated with SiGe clock distribution network
Materials described outside the worked examples.
indium phosphide
InP
silicon germanium
SiGe
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 9,602,125Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a high level schematic diagram of a DAC including a DAC core circuit and a clock tree distribution network;
Figure 2 is a schematic diagram of the DAC core circuit shown in figure 1;
Figure 3 is a schematic diagram of a current switching circuit in one of the DAC core circuit cells; and
Figure 4 is a schematic diagram of the clock tree distribution network shown in figure 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits; a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 1 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 1 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 1 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
The DAC according to claim 1 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 1 wherein the DAC circuit receives twelve input bits.
The DAC according to claim 1 wherein the current switches include most significant bit current switches and least significant bit current switches.
The DAC according to claim 1 wherein the converted analog signal represents the digital bit input signals in both frequency and amplitude.
A digital-to-analog converter (DAC) comprising: a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits, where the converted analog signal represents the digital bits in both frequency and amplitude; 8 Docket No. NGC-00160 (006887-0030) a clock circuit responsive to a sinusoidal clock input signal at one frequency and outputting a clock output signal at another frequency; and a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 11 wherein the DAC core circuit includes a plurality of DAC converter cells each including a buffer that receives one of the digital bit input signals and one of the plurality of split clock signals and a current switch that receives a buffered digital signal from the buffer and outputs a current output signal representative of the digital bit input signal.
The DAC according to claim 11 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a 9 Docket No. NGC-00160 (006887-0030) plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the output of the clock tree are aligned in time.
The DAC according to claim 11 wherein the clock input signal is at 26 GHz and the clock output signal is at 13 GHz.
A digital-to-analog converter (DAC) comprising a DAC core circuit including a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits and a clock tree distribution network providing a plurality of clock signals to the DAC core circuit, wherein the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.
The DAC according to claim 17 wherein the DAC is fabricated using a compound semiconductor materials on silicon (COSMOS) process.
The DAC according to claim 17 wherein the DAC receives a clock input signal at 26 GHz and provides a clock output signal at 13 GHz.
The DAC according to claim 17 wherein the clock tree distribution network includes a plurality of clock tree stages where each stage includes a plurality of buffers that receive a split clock signal and split the clock signal into two clock signals so that the split clock signals at the
Layer stacks claimed or described, ordered top of device to substrate.
wideband InP DAC integrated with SiGe clock distribution network
Materials described outside the worked examples.
indium phosphide
InP
silicon germanium
SiGe
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.