Patent
US 10,855,273High-Side Gate Driver for Gallium Nitride Integrated Circuits
Zhanming Li
US
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Patent
Atlas literature
Patent
US 10,855,273Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-3. Canceled
Canceled
A gate driver circuit for a gallium nitride (GaN) power transistor, comprising: a RS-fli p flo p that receives a first p ulse train at an S in p ut terminal and a second p ulse train at an R in p ut terminal, and p roduces an out p ut p ulse train; a direct-cou pl ed FET logic (DCFL) am pl ifier that am pl ifies the out p ut p ulse train and p roduces a gate driver signal for the GaN p ower transistor; wherein the first p ulse train and the second p ulse train are inde p endentl y controlled signals; wherein the DCFL amplifier comprises: a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point, and an amplifier output point; wherein the first stage input point is connected to a first stage and to the second stage high side input point; and wherein the first stage output point is connected to the second stage low side input point. Currently amended
5-7. Canceled
Canceled
The gate driver circuit of claim [[1]]4, wherein the RS-flipflop is implemented on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; wherein the two DHEMTs are configured as nonlinear loads for the main RS-flipflop transistors. Currently amended
The gate driver circuit of claim 8, wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100 ± 50):(30 ± 15):(1 ± 0.5), respectively. Previously presented
The gate driver circuit of claim 8, further comprising a device that outputs the first pulse train and the second pulse train; wherein a pulse width of the first pulse train is within a range of about 5 ns to 15 ns; and wherein a pulse width of the second pulse train is within a range of about 5 ns to 15 ns. Original
13-18. Canceled
Canceled
A method for im pl ementing a g ate driver circuit for a GaN p ower transistor, com p rising: using a RS-fli p flo p to receive a first p ulse train at an S in p ut terminal, receive a second p ulse train at an R input terminal, and produce an output pulse train; amplifying the output pulse train to produce a gate driver signal for the GaN power transistor; wherein the first pulse train and the second pulse train are independently controlled signals; the method further comprising implementing the RS-flipflop on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein channel width and are arranged back-to-back as two of the EHEMTs are of a small channel width wherein the two DHEMTs are configured as non-linear Currently amended
The method of claim 19, wherein a ratio of a large channel width, the two EHEMTs of a small 50):(30 ± 15):(1 ± 0.5), respectively. Previously
21-23. Canceled
Canceled a first two of the EHEMTs are of a large main RS-flipflop transistors; wherein a second and are arranged as R and S input transistors; loads for the main RS-flipflop transistors. transistor channel widths for the two EHEMTs of channel width, and the two DHEMTs is (100 ± presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN gate driver circuit with DCFL amplifier
No layer stack recorded.
GaN monolithic integrated circuit RS-flipflop with EHEMTs and DHEMTs
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 3–15 V | — |
Thickness | 800–2000 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,855,273Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-3. Canceled
Canceled
A gate driver circuit for a gallium nitride (GaN) power transistor, comprising: a RS-fli p flo p that receives a first p ulse train at an S in p ut terminal and a second p ulse train at an R in p ut terminal, and p roduces an out p ut p ulse train; a direct-cou pl ed FET logic (DCFL) am pl ifier that am pl ifies the out p ut p ulse train and p roduces a gate driver signal for the GaN p ower transistor; wherein the first p ulse train and the second p ulse train are inde p endentl y controlled signals; wherein the DCFL amplifier comprises: a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point, and an amplifier output point; wherein the first stage input point is connected to a first stage and to the second stage high side input point; and wherein the first stage output point is connected to the second stage low side input point. Currently amended
5-7. Canceled
Canceled
The gate driver circuit of claim [[1]]4, wherein the RS-flipflop is implemented on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; wherein the two DHEMTs are configured as nonlinear loads for the main RS-flipflop transistors. Currently amended
The gate driver circuit of claim 8, wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100 ± 50):(30 ± 15):(1 ± 0.5), respectively. Previously presented
The gate driver circuit of claim 8, further comprising a device that outputs the first pulse train and the second pulse train; wherein a pulse width of the first pulse train is within a range of about 5 ns to 15 ns; and wherein a pulse width of the second pulse train is within a range of about 5 ns to 15 ns. Original
13-18. Canceled
Canceled
A method for im pl ementing a g ate driver circuit for a GaN p ower transistor, com p rising: using a RS-fli p flo p to receive a first p ulse train at an S in p ut terminal, receive a second p ulse train at an R input terminal, and produce an output pulse train; amplifying the output pulse train to produce a gate driver signal for the GaN power transistor; wherein the first pulse train and the second pulse train are independently controlled signals; the method further comprising implementing the RS-flipflop on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein channel width and are arranged back-to-back as two of the EHEMTs are of a small channel width wherein the two DHEMTs are configured as non-linear Currently amended
The method of claim 19, wherein a ratio of a large channel width, the two EHEMTs of a small 50):(30 ± 15):(1 ± 0.5), respectively. Previously
21-23. Canceled
Canceled a first two of the EHEMTs are of a large main RS-flipflop transistors; wherein a second and are arranged as R and S input transistors; loads for the main RS-flipflop transistors. transistor channel widths for the two EHEMTs of channel width, and the two DHEMTs is (100 ± presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN gate driver circuit with DCFL amplifier
No layer stack recorded.
GaN monolithic integrated circuit RS-flipflop with EHEMTs and DHEMTs
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 3–15 V | — |
Thickness | 800–2000 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,855,273Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-3. Canceled
Canceled
A gate driver circuit for a gallium nitride (GaN) power transistor, comprising: a RS-fli p flo p that receives a first p ulse train at an S in p ut terminal and a second p ulse train at an R in p ut terminal, and p roduces an out p ut p ulse train; a direct-cou pl ed FET logic (DCFL) am pl ifier that am pl ifies the out p ut p ulse train and p roduces a gate driver signal for the GaN p ower transistor; wherein the first p ulse train and the second p ulse train are inde p endentl y controlled signals; wherein the DCFL amplifier comprises: a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point, and an amplifier output point; wherein the first stage input point is connected to a first stage and to the second stage high side input point; and wherein the first stage output point is connected to the second stage low side input point. Currently amended
5-7. Canceled
Canceled
The gate driver circuit of claim [[1]]4, wherein the RS-flipflop is implemented on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; wherein the two DHEMTs are configured as nonlinear loads for the main RS-flipflop transistors. Currently amended
The gate driver circuit of claim 8, wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100 ± 50):(30 ± 15):(1 ± 0.5), respectively. Previously presented
The gate driver circuit of claim 8, further comprising a device that outputs the first pulse train and the second pulse train; wherein a pulse width of the first pulse train is within a range of about 5 ns to 15 ns; and wherein a pulse width of the second pulse train is within a range of about 5 ns to 15 ns. Original
13-18. Canceled
Canceled
A method for im pl ementing a g ate driver circuit for a GaN p ower transistor, com p rising: using a RS-fli p flo p to receive a first p ulse train at an S in p ut terminal, receive a second p ulse train at an R input terminal, and produce an output pulse train; amplifying the output pulse train to produce a gate driver signal for the GaN power transistor; wherein the first pulse train and the second pulse train are independently controlled signals; the method further comprising implementing the RS-flipflop on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein channel width and are arranged back-to-back as two of the EHEMTs are of a small channel width wherein the two DHEMTs are configured as non-linear Currently amended
The method of claim 19, wherein a ratio of a large channel width, the two EHEMTs of a small 50):(30 ± 15):(1 ± 0.5), respectively. Previously
21-23. Canceled
Canceled a first two of the EHEMTs are of a large main RS-flipflop transistors; wherein a second and are arranged as R and S input transistors; loads for the main RS-flipflop transistors. transistor channel widths for the two EHEMTs of channel width, and the two DHEMTs is (100 ± presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN gate driver circuit with DCFL amplifier
No layer stack recorded.
GaN monolithic integrated circuit RS-flipflop with EHEMTs and DHEMTs
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 3–15 V | — |
Thickness | 800–2000 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,855,273Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-3. Canceled
Canceled
A gate driver circuit for a gallium nitride (GaN) power transistor, comprising: a RS-fli p flo p that receives a first p ulse train at an S in p ut terminal and a second p ulse train at an R in p ut terminal, and p roduces an out p ut p ulse train; a direct-cou pl ed FET logic (DCFL) am pl ifier that am pl ifies the out p ut p ulse train and p roduces a gate driver signal for the GaN p ower transistor; wherein the first p ulse train and the second p ulse train are inde p endentl y controlled signals; wherein the DCFL amplifier comprises: a first stage input point, a first stage output point, a second stage high side input point, a second stage low side input point, and an amplifier output point; wherein the first stage input point is connected to a first stage and to the second stage high side input point; and wherein the first stage output point is connected to the second stage low side input point. Currently amended
5-7. Canceled
Canceled
The gate driver circuit of claim [[1]]4, wherein the RS-flipflop is implemented on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein a first two of the EHEMTs are of a large channel width and are arranged back-to-back as main RS-flipflop transistors; wherein a second two of the EHEMTs are of a small channel width and are arranged as R and S input transistors; wherein the two DHEMTs are configured as nonlinear loads for the main RS-flipflop transistors. Currently amended
The gate driver circuit of claim 8, wherein a ratio of transistor channel widths for the two EHEMTs of a large channel width, the two EHEMTs of a small channel width, and the two DHEMTs is (100 ± 50):(30 ± 15):(1 ± 0.5), respectively. Previously presented
The gate driver circuit of claim 8, further comprising a device that outputs the first pulse train and the second pulse train; wherein a pulse width of the first pulse train is within a range of about 5 ns to 15 ns; and wherein a pulse width of the second pulse train is within a range of about 5 ns to 15 ns. Original
13-18. Canceled
Canceled
A method for im pl ementing a g ate driver circuit for a GaN p ower transistor, com p rising: using a RS-fli p flo p to receive a first p ulse train at an S in p ut terminal, receive a second p ulse train at an R input terminal, and produce an output pulse train; amplifying the output pulse train to produce a gate driver signal for the GaN power transistor; wherein the first pulse train and the second pulse train are independently controlled signals; the method further comprising implementing the RS-flipflop on a GaN monolithic integrated circuit; wherein the RS-flipflop comprises: four EHEMTs and two DHEMTs; wherein channel width and are arranged back-to-back as two of the EHEMTs are of a small channel width wherein the two DHEMTs are configured as non-linear Currently amended
The method of claim 19, wherein a ratio of a large channel width, the two EHEMTs of a small 50):(30 ± 15):(1 ± 0.5), respectively. Previously
21-23. Canceled
Canceled a first two of the EHEMTs are of a large main RS-flipflop transistors; wherein a second and are arranged as R and S input transistors; loads for the main RS-flipflop transistors. transistor channel widths for the two EHEMTs of channel width, and the two DHEMTs is (100 ± presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN gate driver circuit with DCFL amplifier
No layer stack recorded.
GaN monolithic integrated circuit RS-flipflop with EHEMTs and DHEMTs
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 3–15 V | — |
Thickness | 800–2000 µm |
Related documents with shared materials, methods, properties, or citations.
| — |
Thickness | 200–2000 µm | — |
Thickness | 7–20 µm | — |
| — |
Thickness | 200–2000 µm | — |
Thickness | 7–20 µm | — |
| — |
Thickness | 200–2000 µm | — |
Thickness | 7–20 µm | — |
| — |
Thickness | 200–2000 µm | — |
Thickness | 7–20 µm | — |