GaN HEMT POWER TRANSISTOR PULSE LEVELING CIRCUIT

Benone Achiriloaie

Patent

Atlas literature

Patent

US 8,786,342

GaN HEMT POWER TRANSISTOR PULSE LEVELING CIRCUIT

Benone Achiriloaie

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1, a block diagram of a circuit 100 is shown in accordance with an embodiment of the present invention. 20 The circuit 100 generally comprises a block (or …

FIG. 2

FIG. 2 is a more detailed diagram of the circuit of

FIG. 3

FIG. 3 is a waveform of a voltage applied to a gate of a device under test; and

FIG. 4

FIGS. 4a-4c, a number of waveform diagrams 5 are shown. In general, the signal V G may be shifted up or down by varying the strength of the supply voltage. The …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

6 independent · 4 dependent

1
IndependentGaN HEMT power transistor pulse leveling circuit
An apparatus comprising: an RF circuit conﬁgured to generate (i) an output signal and (ii) a ﬁrst intermediate signal, in response to (i) an input signal and (ii) a control signal; 5 a converter circuit conﬁgured to generate a second intermediate signal in response to said ﬁrst intermediate signal; an ampliﬁer conﬁgured to generate a third intermediate signal in response to the second intermediate signal; and a an RC delay circuit conﬁgured to generate said control 10 signal in response to the third intermediate signal, wherein said RF circuit generates said output signal having a ﬂattened response by providing pulse shaping in response to said control signal.
1. 2
  Dependent← claim 1GaN HEMT power transistor pulse leveling circuit
  The apparatus according to claim 1, wherein said RC delay circuit comprises a ﬁrst resistor, a second resistor, and a capacitor, wherein said ﬁrst resistor and said second resistor are sized to create said ﬂattened response of 5 said output signal.
2. 3
  Dependent← claim 1GaN HEMT power transistor pulse leveling circuit
  The apparatus according to claim 1, wherein said ampliﬁer ci rc ui t comprises a ﬁrst operational ampliﬁer and a second operational ampliﬁer.
3. 6
  Dependent← claim 1GaN HEMTGaN HEMT power transistor pulse leveling circuit
  The apparatus according to claim 1, wherein said RF circuit comprises an RF matching circuit conﬁgured to test a GaN HEMT power transistor.
4. 8
  Dependent← claim 1GaN HEMT power transistor pulse leveling circuit
  8. The apparatus according to claim 1, wherein said RC delay circuit comprises one or more resistors and one or more capacitors.
4
IndependentGaN HEMT power transistor pulse leveling circuit
The apparatus according to claim ± 3, wherein said ﬁrst operational ampliﬁer increases a gate voltage of a device under test.
5
IndependentGaN HEMT power transistor pulse leveling circuit
The apparatus according to claim + 3, wherein said second circ ui t o p erational am p liﬁer buﬀers current to provide isolation.
7
Independent
7.. canceled
9
IndependentGaN HEMT power transistor pulse leveling circuit
9. An apparatus comprising: means for generating (i) an output signal and (ii) a ﬁrst intermediate signal, in response to (i) an input signal and (ii) a control signal; 5 means for generating a second intermediate signal in response to said ﬁrst intermediate signal; 4 means for generating a third intermediate signal in response to the second intermediate signal; and means for generating said control signal usin g an RC 10 delay circuit in response to the third intermediate signal, wherein said apparatus generates said output signal having a ﬂattened response by providing pulse shaping in response to said control signal.
10
IndependentGaN HEMTGaN HEMT power transistor pulse leveling circuit
10. A method for leveling pulses in a signal generated by a GaN HEMT power transistor, comprising the steps of: (A) generating (i) an output signal and (ii) a ﬁrst 5 intermediate signal, in response to (i) an input signal and (ii) a control signal; (B) generating a second intermediate signal in response to said ﬁrst intermediate signal; (C) generating a third intermediate signal in response 10 to the second intermediate signal; and (D) generating said control signal in response to the third intermediate signal usin g an RC delay circuit, wherein said method generates said output signal having a ﬂattened response by providing pulse shaping in response to said control signal.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

GaN HEMT power transistor pulse leveling circuit

GaN HEMTdevice under test (GaN HEMT power transistor)

RC delay circuit (generates control signal from third intermediate signal)RC delay circuit (generates control signal from third intermediate signal)

amplifier circuit (generates third intermediate signal from second intermediate signal)amplifier circuit (generates third intermediate signal from second intermediate signal)

converter circuit (power/voltage converter, generates second intermediate signal from first intermediate signal)converter circuit (power/voltage converter, generates second intermediate signal from first intermediate signal)

RF circuit (generates output signal and first intermediate signal, controlled by control signal)

Materials

Materials described outside the worked examples.

GaN HEMT

Device Under Test Transistor Material

Why these are connected

Related documents with shared materials, methods, properties, or citations.

GaN HEMT POWER TRANSISTOR PULSE LEVELING CIRCUIT | Matter42 Literature